implement interconnect for simt cacheHEADmaster

+ Actual cache still missing, lol

+ Initial performance numbers aren't too promising compared to
  simt_riscv64 or even simple_mesh1d, but there's a somewhat
  increased latency due to registering inputs and the shared req
  logic which can likely be improved. Will have to dig into this a
  bit further

1 files changed, 1 insertions, 0 deletions

diff --git a/src/cache/source.mk b/src/cache/source.mk
new file mode 100644
index 0000000..20f0bf9
--- /dev/null
+++ b/src/cache/source.mk
@@ -0,0 +1 @@
+GRAN_SOURCES += src/cache/simt_cache.c