implement interconnect for simt cacheHEADmaster

+ Actual cache still missing, lol

+ Initial performance numbers aren't too promising compared to
  simt_riscv64 or even simple_mesh1d, but there's a somewhat
  increased latency due to registering inputs and the shared req
  logic which can likely be improved. Will have to dig into this a
  bit further

6 files changed, 421 insertions, 0 deletions

diff --git a/include/gran/cache/simt_cache.h b/include/gran/cache/simt_cache.h
new file mode 100644
index 0000000..8939d1a
--- /dev/null
+++ b/include/gran/cache/simt_cache.h
@@ -0,0 +1,9 @@
+#ifndef GRAN_SIMT_CACHE_H
+#define GRAN_SIMT_CACHE_H
+
+#include <gran/component.h>
+
+struct component *create_simt_cache(uint64_t rcv, size_t num_lanes, struct component *mem);
+void simt_cache_connect_lane(struct component *c, size_t i, struct component *l);
+
+#endif /* GRAN_SIMT_CACHE_H */
diff --git a/src/cache/simt_cache.c b/src/cache/simt_cache.c
new file mode 100644
index 0000000..327746d
--- /dev/null
+++ b/src/cache/simt_cache.c
@@ -0,0 +1,231 @@
+#include <gran/cache/simt_cache.h>
+
+#define VEC_NAME lanes
+#define VEC_TYPE struct component *
+#include <conts/vec.h>
+
+struct req {
+	struct reg reg;
+	bool queued;
+};
+
+#define VEC_NAME reqs
+#define VEC_TYPE struct req
+#include <conts/vec.h>
+
+struct simt_cache {
+	struct component component;
+	struct component *mem;
+	struct lanes lanes;
+	struct reqs reqs;
+	uint64_t rcv;
+	uint32_t rr;
+};
+
+static stat simt_cache_ext_send(struct simt_cache *cache, size_t i, struct req *r)
+{
+	assert(r->reg.busy);
+
+	/* do fixups for sending */
+	struct packet p = r->reg.pkt;
+	if (is_set(&p, PACKET_READ))
+		p.mask = ~0ULL;
+
+	p.from = cache->rcv | i;
+	return SEND(&cache->component, cache->mem, p);
+}
+
+static stat simt_cache_clock(struct simt_cache *cache)
+{
+	struct req *shared = reqs_at(&cache->reqs, cache->rr);
+
+	/* start sending out queued stuff */
+	for (size_t i = 0; i < reqs_len(&cache->reqs); ++i) {
+		struct req *r = reqs_at(&cache->reqs, i);
+		if (!r->queued)
+			continue;
+
+		if (!r->reg.busy)
+			continue;
+
+		struct packet *p = &r->reg.pkt;
+
+		/* if we're trying to read from the same address as the shared reg and
+		 * we're not currently in charge of the shared reg, we can stop queuing
+		 * as shared reg will take care of our request as well */
+		if (shared->reg.busy
+				&& is_set(&shared->reg.pkt, PACKET_READ)
+				&& is_set(p, PACKET_READ)
+				&& p->to == shared->reg.pkt.to
+				&& i != cache->rr) {
+			r->queued = false;
+			continue;
+		}
+
+		size_t block_idx = (p->to / 64) % reqs_len(&cache->reqs);
+
+		/* check if the address in this packet can be directly sent to
+		 * the corresponding block port, i.e. the 64 byte block matches
+		 * our index. Alternatively, if we're currently holding the
+		 * shared register, we can send to any block index */
+		if (block_idx == i || cache->rr == i) {
+			stat ok = simt_cache_ext_send(cache, i, r);
+			if (ok == OK) {
+				r->queued = false;
+				continue;
+			}
+
+			if (ok == EBUSY)
+				continue;
+
+			/* something went wrong */
+			return ok;
+		}
+	}
+
+	/* if we're not waiting on a shared request, move forward to next active
+	 * element to prevent deadlocks */
+	if (!shared->reg.busy)
+	for (size_t i = 0; i < reqs_len(&cache->reqs); ++i) {
+		cache->rr = (cache->rr + 1) % reqs_len(&cache->reqs);
+		if (reqs_at(&cache->reqs, cache->rr)->reg.busy)
+			break;
+	}
+
+	return OK;
+}
+
+static stat simt_cache_broadcast(struct simt_cache *cache, struct packet pkt)
+{
+	assert(is_set(&pkt, PACKET_READ));
+	for (size_t i = 0; i < reqs_len(&cache->reqs); ++i) {
+		struct req *r = reqs_at(&cache->reqs, i);
+		if (!r->reg.busy)
+			continue;
+
+		if (r->reg.pkt.to != pkt.from)
+			continue;
+
+		if (!is_set(&r->reg.pkt, PACKET_READ))
+			continue;
+
+		struct component *lane = *lanes_at(&cache->lanes, i);
+
+		pkt.mask = r->reg.pkt.mask;
+		pkt.to   = r->reg.pkt.from;
+
+		stat ok = SEND(&cache->component, lane, pkt);
+
+		/* no reason for core to be blocked */
+		assert(ok == OK);
+
+		r->reg.busy = false;
+
+		/* queued might be set at this point if there was an attempt to
+		 * send a packet that failed, but we can deal with it here */
+		r->queued   = false;
+	}
+
+	return OK;
+}
+
+static stat simt_cache_handle_response(struct simt_cache *cache, struct packet pkt)
+{
+	/** @todo handle external requests, this currently only accepts
+	 * responses and an IPI would not work with this */
+	assert(!is_set(&pkt, PACKET_ERROR));
+	assert(is_set(&pkt, PACKET_DONE));
+	assert(is_set(&pkt, PACKET_READ) ? pkt.mask == ~0ULL : 1);
+
+	uint32_t idx = (uint32_t)pkt.to;
+	if (cache->rr == idx) {
+		/* round robin satisfied, move to next element */
+		cache->rr = (cache->rr + 1) % reqs_len(&cache->reqs);
+		if (is_set(&pkt, PACKET_READ))
+			return simt_cache_broadcast(cache, pkt);
+	}
+
+	struct req *r = reqs_at(&cache->reqs, idx);
+	assert(!r->queued);
+	assert(r->reg.busy);
+	assert(r->reg.pkt.to == pkt.from);
+
+	/* restore rewritten fields */
+	pkt.mask = r->reg.pkt.mask;
+	pkt.to   = r->reg.pkt.from;
+
+	r->reg.busy = false;
+
+	struct component *lane = *lanes_at(&cache->lanes, idx);
+	stat ok = SEND(&cache->component, lane, pkt);
+	assert(ok == OK);
+	return ok;
+}
+
+static stat simt_cache_receive(struct simt_cache *cache,
+		struct component *from, struct packet pkt)
+{
+	if (cache->mem == from)
+		return simt_cache_handle_response(cache, pkt);
+
+	uint32_t idx = pkt.from >> 32;
+	struct component *lane = *lanes_at(&cache->lanes, idx);
+	if (lane != from)
+		return ENOSUCH;
+
+	struct req *r = reqs_at(&cache->reqs, idx);
+	if (r->reg.busy)
+		return EBUSY;
+
+	assert(r->queued == false);
+	r->reg.busy = true;
+	r->reg.pkt = pkt;
+	r->queued = true;
+
+	return OK;
+}
+
+static void simt_cache_destroy(struct simt_cache *cache)
+{
+	lanes_destroy(&cache->lanes);
+	reqs_destroy(&cache->reqs);
+	free(cache);
+}
+
+struct component *create_simt_cache(uint64_t rcv, size_t num_lanes, struct component *mem)
+{
+	struct simt_cache *cache = calloc(1, sizeof(struct simt_cache));
+	if (!cache)
+		return NULL;
+
+	cache->component.clock = (clock_callback)simt_cache_clock;
+	cache->component.receive = (receive_callback)simt_cache_receive;
+	cache->component.destroy = (destroy_callback)simt_cache_destroy;
+
+	cache->lanes = lanes_create(num_lanes);
+	cache->reqs  = reqs_create(num_lanes);
+	cache->mem   = mem;
+	cache->rcv   = rcv;
+	cache->rr    = 0;
+
+	struct req empty = {
+		.reg = {
+			.pkt = {},
+			.busy = false
+		},
+		.queued = false
+	};
+
+	for (size_t i = 0; i < num_lanes; ++i) {
+		reqs_append(&cache->reqs, empty);
+		lanes_append(&cache->lanes, NULL);
+	}
+
+	return &cache->component;
+}
+
+void simt_cache_connect_lane(struct component *c, size_t i, struct component *e)
+{
+	struct simt_cache *cache = (struct simt_cache *)c;
+	*lanes_at(&cache->lanes, i) = e;
+}
diff --git a/src/cache/source.mk b/src/cache/source.mk
new file mode 100644
index 0000000..20f0bf9
--- /dev/null
+++ b/src/cache/source.mk
@@ -0,0 +1 @@
+GRAN_SOURCES += src/cache/simt_cache.c
diff --git a/tests/simt_cache/sim.c b/tests/simt_cache/sim.c
new file mode 100644
index 0000000..780ef80
--- /dev/null
+++ b/tests/simt_cache/sim.c
@@ -0,0 +1,102 @@
+#include <assert.h>
+
+#include <gran/root.h>
+#include <gran/mem/simple_mem.h>
+#include <gran/bus/simple_bus.h>
+#include <gran/uart/simple_uart.h>
+#include <gran/mesh/node1d.h>
+#include <gran/cpu/riscv/simple_riscv64.h>
+#include <gran/cache/simt_cache.h>
+
+#include "../build/tests/simt_cache/test.inc"
+
+static stat build_simt(struct clock_domain *clk, uint16_t clusters, uint16_t lanes)
+{
+	struct component **mesh = calloc(clusters + 1, sizeof(struct component *));
+	assert(mesh);
+
+	for (int i = 1; i < clusters + 1; ++i) {
+		struct component *node = create_mesh_node1d(i, 3);
+		clock_domain_add(clk, node);
+		mesh[i] = node;
+
+		struct component *mem = create_simple_mem(4096);
+		init_simple_mem(mem, 0,
+				build_tests_simt_cache_test_inc_bin_len,
+				build_tests_simt_cache_test_inc_bin);
+
+		clock_domain_add(clk, mem);
+
+		uint64_t icache_rcv = mesh1d_addr(i, 0, 0);
+		struct component *icache = create_simt_cache(icache_rcv, lanes, node);
+		clock_domain_add(clk, icache);
+
+		uint64_t dcache_rcv = mesh1d_addr(i, 1, 0);
+		struct component *dcache = create_simt_cache(dcache_rcv, lanes, node);
+		clock_domain_add(clk, dcache);
+
+		for (int j = 0; j < lanes; ++j) {
+			struct component *rv64 = create_simple_riscv64(
+					(uint64_t)j << 32,
+					mesh1d_addr(i, 2, 0),
+					icache,
+					dcache
+			);
+
+			simple_riscv64_set_reg(rv64, 10, i); /* a0 */
+			simple_riscv64_set_reg(rv64, 11, j); /* a1 */
+			simple_riscv64_set_reg(rv64, 12, clusters); /* a2 */
+			simple_riscv64_set_reg(rv64, 13, lanes); /* a3 */
+			clock_domain_add(clk, rv64);
+
+			simt_cache_connect_lane(icache, j, rv64);
+			simt_cache_connect_lane(dcache, j, rv64);
+		}
+
+		mesh_node1d_connect(node, icache, 0);
+		mesh_node1d_connect(node, dcache, 1);
+		mesh_node1d_connect(node, mem, 2);
+	}
+
+	/* extra I/O node */
+	struct component *node = create_mesh_node1d(0, 2);
+	clock_domain_add(clk, node);
+	mesh[0] = node;
+
+	struct component *uart = create_simple_uart();
+	clock_domain_add(clk, uart);
+	mesh_node1d_connect(node, uart, 0);
+
+	struct component *mem = create_simple_mem(4096);
+	clock_domain_add(clk, mem);
+	mesh_node1d_connect(node, mem, 1);
+
+	for (int i = 0; i < clusters + 1; ++i) {
+		if (i - 1 >= 0)
+			mesh_node1d_connect_south(mesh[i], mesh[i - 1]);
+
+		if (i + 1 < clusters + 1)
+			mesh_node1d_connect_north(mesh[i], mesh[i + 1]);
+	}
+
+	free(mesh);
+	return OK;
+}
+
+int main()
+{
+	struct clock_domain *clk = create_clock_domain(NS(1));
+
+	/* one cluster with four cores + mem for each core (should
+	 * instructions be fetched from cluster local mem?) */
+	stat r = build_simt(clk, 8, 8);
+	assert(r == OK);
+
+	struct gran_root *root = create_root();
+	root_add_clock(root, clk);
+
+	r = root_run(root);
+	assert(r == OK);
+
+	destroy_root(root);
+}
diff --git a/tests/simt_cache/source.mk b/tests/simt_cache/source.mk
new file mode 100644
index 0000000..c9b5877
--- /dev/null
+++ b/tests/simt_cache/source.mk
@@ -0,0 +1,11 @@
+SIMT_CACHE	:= tests/simt_cache
+SIMT_CACHE_SIM	:= $(SIMT_CACHE)/sim.c
+
+TESTS += $(SIMT_CACHE)/sim
+
+.PHONY: $(SIMT_CACHE)/sim
+$(SIMT_CACHE)/sim: $(SIMT_CACHE_SIM) libgran.a
+	mkdir -p build/$(SIMT_CACHE)
+	./scripts/gen-rv64-fw -d build -o $(SIMT_CACHE)/test.inc $(SIMT_CACHE)/test.c
+	$(COMPILE_TEST) $(SIMT_CACHE_SIM) libgran.a -o build/$@
+	./scripts/gen-report -d build $@
diff --git a/tests/simt_cache/test.c b/tests/simt_cache/test.c
new file mode 100644
index 0000000..df86774
--- /dev/null
+++ b/tests/simt_cache/test.c
@@ -0,0 +1,67 @@
+#include <stdint.h>
+
+__attribute__((always_inline))
+static inline uint64_t mesh1d_addr(uint16_t cluster, uint16_t elem,
+                                   uint32_t off)
+{
+	return ((uint64_t)cluster << 48) | ((uint64_t)elem << 32) | off;
+}
+
+__attribute__((always_inline))
+static inline void print_int8(volatile char *uart, unsigned x)
+{
+	char lo_nibble = (x >> 0) & 0xf;
+	char hi_nibble = (x >> 4) & 0xf;
+
+	*uart = hi_nibble < 10 ? hi_nibble + '0' : (hi_nibble - 10) + 'a';
+	*uart = lo_nibble < 10 ? lo_nibble + '0' : (lo_nibble - 10) + 'a';
+}
+
+__attribute__((always_inline))
+static inline void print_addr(volatile char *uart, unsigned x, unsigned y)
+{
+	*uart = '(';
+	print_int8(uart, x);
+	*uart = ',';
+	*uart = ' ';
+	print_int8(uart, y);
+	*uart = ')';
+	*uart = '\n';
+}
+
+__attribute__((always_inline))
+static inline uint64_t wrap(unsigned x, unsigned X)
+{
+	return x + 1 >= X ? 0 : x + 1;
+}
+
+__attribute__((always_inline))
+static inline uint64_t next_idx(unsigned x, unsigned y, unsigned X, unsigned Y)
+{
+	unsigned yi = wrap(y, Y);
+	unsigned xi = yi < y ? wrap(x, X) : x;
+
+	return mesh1d_addr(xi, yi, 0);
+}
+
+void _start(unsigned x, unsigned y, unsigned X, unsigned Y)
+{
+	volatile char *uart = (char *)mesh1d_addr(0, 0, 0);
+	volatile uint64_t *control = (uint64_t *)mesh1d_addr(0, 1, 0);
+
+	if (x == 1 && y == 0) {
+		goto do_work;
+	} else {
+		while (*control != mesh1d_addr(x, y, 0)) {}
+	}
+
+do_work:
+	print_addr(uart, x, y);
+	*control = next_idx(x, y, X, Y);
+
+	if (x == X - 1 && y == Y - 1)
+		asm ("ebreak");
+
+	/* otherwise just loop */
+	while (1) {}
+}