From ead834152ffec8559eb37e9887d215fcf60338a2 Mon Sep 17 00:00:00 2001 From: Kimplul Date: Wed, 24 Dec 2025 00:38:37 +0200 Subject: implement interconnect for simt cache + Actual cache still missing, lol + Initial performance numbers aren't too promising compared to simt_riscv64 or even simple_mesh1d, but there's a somewhat increased latency due to registering inputs and the shared req logic which can likely be improved. Will have to dig into this a bit further --- src/cache/source.mk | 1 + 1 file changed, 1 insertion(+) create mode 100644 src/cache/source.mk (limited to 'src/cache/source.mk') diff --git a/src/cache/source.mk b/src/cache/source.mk new file mode 100644 index 0000000..20f0bf9 --- /dev/null +++ b/src/cache/source.mk @@ -0,0 +1 @@ +GRAN_SOURCES += src/cache/simt_cache.c -- cgit v1.3