implement interconnect for simt cacheHEADmaster

+ Actual cache still missing, lol

+ Initial performance numbers aren't too promising compared to
  simt_riscv64 or even simple_mesh1d, but there's a somewhat
  increased latency due to registering inputs and the shared req
  logic which can likely be improved. Will have to dig into this a
  bit further

1 files changed, 9 insertions, 0 deletions

diff --git a/include/gran/cache/simt_cache.h b/include/gran/cache/simt_cache.h
new file mode 100644
index 0000000..8939d1a
--- /dev/null
+++ b/include/gran/cache/simt_cache.h
@@ -0,0 +1,9 @@
+#ifndef GRAN_SIMT_CACHE_H
+#define GRAN_SIMT_CACHE_H
+
+#include <gran/component.h>
+
+struct component *create_simt_cache(uint64_t rcv, size_t num_lanes, struct component *mem);
+void simt_cache_connect_lane(struct component *c, size_t i, struct component *l);
+
+#endif /* GRAN_SIMT_CACHE_H */