From ead834152ffec8559eb37e9887d215fcf60338a2 Mon Sep 17 00:00:00 2001 From: Kimplul Date: Wed, 24 Dec 2025 00:38:37 +0200 Subject: implement interconnect for simt cache + Actual cache still missing, lol + Initial performance numbers aren't too promising compared to simt_riscv64 or even simple_mesh1d, but there's a somewhat increased latency due to registering inputs and the shared req logic which can likely be improved. Will have to dig into this a bit further --- include/gran/cache/simt_cache.h | 9 +++++++++ 1 file changed, 9 insertions(+) create mode 100644 include/gran/cache/simt_cache.h (limited to 'include') diff --git a/include/gran/cache/simt_cache.h b/include/gran/cache/simt_cache.h new file mode 100644 index 0000000..8939d1a --- /dev/null +++ b/include/gran/cache/simt_cache.h @@ -0,0 +1,9 @@ +#ifndef GRAN_SIMT_CACHE_H +#define GRAN_SIMT_CACHE_H + +#include + +struct component *create_simt_cache(uint64_t rcv, size_t num_lanes, struct component *mem); +void simt_cache_connect_lane(struct component *c, size_t i, struct component *l); + +#endif /* GRAN_SIMT_CACHE_H */ -- cgit v1.3