diff options
Diffstat (limited to 'tb')
| -rw-r--r-- | tb/Makefile | 14 | ||||
| -rw-r--r-- | tb/data/rv2insn.S | 6 | ||||
| -rw-r--r-- | tb/rv2insn_tb.sv | 42 | ||||
| -rw-r--r-- | tb/sched_tb.sv | 84 |
4 files changed, 76 insertions, 70 deletions
diff --git a/tb/Makefile b/tb/Makefile new file mode 100644 index 0000000..a76747f --- /dev/null +++ b/tb/Makefile @@ -0,0 +1,14 @@ +all: rv2insn sched + +.PHONY: sched +sched: sched_tb.sv ../src/sched.sv ../src/common.svh + verilator --Mdir sched_objdir --assert --trace --binary -I../src sched_tb.sv + ./sched_objdir/Vsched_tb + +.PHONY: rv2insn +rv2insn: rv2insn_tb.sv ../src/rv2insn.sv ../src/common.svh + riscv32-unknown-elf-gcc -ffreestanding -nostdlib -march=rv32i -mabi=ilp32 \ + -Wl,-Ttext=0 data/rv2insn.S -o rv2insn + riscv32-unknown-elf-objcopy -O verilog rv2insn rv2insn.hex + verilator --Mdir rv2insn_objdir --assert --trace --binary -I../src rv2insn_tb.sv + ./rv2insn_objdir/Vrv2insn_tb diff --git a/tb/data/rv2insn.S b/tb/data/rv2insn.S new file mode 100644 index 0000000..a0ee610 --- /dev/null +++ b/tb/data/rv2insn.S @@ -0,0 +1,6 @@ +.global _start +_start: +add x1, x2, x3 +addi x4, x5, 123 +sub x6, x7, x8 +addi x9, x10, -456 diff --git a/tb/rv2insn_tb.sv b/tb/rv2insn_tb.sv new file mode 100644 index 0000000..14a0249 --- /dev/null +++ b/tb/rv2insn_tb.sv @@ -0,0 +1,42 @@ +`include "common.svh" + +module rv2insn_tb; + +logic clk; +logic rst_n; + +xlen_t pc; +logic[7:0] rv[4*4]; +insn_t[3:0] que; + +function automatic rv_t[3:0] unp2p(logic[7:0] in[4*4]); + logic [15:0][7:0] conversion; + for (int i = 0; i < 4 * 4; ++i) begin + conversion[i] = in[i]; + end + return conversion; +endfunction + +rv2insn #( + .QUE_DEPTH(4), + .ALU_COUNT(2) +) rv2insn ( + .clk_i(clk), + .rst_ni(rst_n), + .pc_i(pc), + .rv_i(unp2p(rv)), + .que_o(que) +); + +initial begin + $dumpfile("rv2insn_tb.vcd"); + $dumpvars(); + $readmemh("rv2insn.hex", rv); + + clk = 0; + rst_n = 0; + + #10 rst_n = 1; + #10 $finish; +end +endmodule diff --git a/tb/sched_tb.sv b/tb/sched_tb.sv index 8db66b3..036464e 100644 --- a/tb/sched_tb.sv +++ b/tb/sched_tb.sv @@ -2,62 +2,11 @@ module sched_tb; -typedef enum logic [7:0] { - NOP = `NOP, - R0, - R1, - R2, - R3, - R4, - R5, - R6, - R7, - R8, - R9, - R10, - R11, - R12, - R13, - R14, - R15, - R16, - R17, - R18, - R19, - R20, - R21, - R22, - R23, - R24, - R25, - R26, - R27, - R28, - R29, - R30, - R31, - - ALU0, - ALU1 -} port_t; - -typedef logic [19:0] op_t; - -typedef struct packed { - port_t src; - port_t dst; -} mov_t; - -typedef struct packed { - mov_t[1:0] in; - mov_t out; - op_t op; -} insn_t; - typedef struct packed { mov_t[1:0] in; mov_t[0:0] out; op_t op; + imm_t imm; } slot_t; slot_t[1:0] prev_slots; @@ -69,9 +18,6 @@ sched #( .QUE_DEPTH(3), .SLOT_COUNT(2), .SLOT_DEPTH(1), - .port_t(port_t), - .mov_t(mov_t), - .insn_t(insn_t), .slot_t(slot_t) ) sched ( .que_i(prev_que), @@ -80,16 +26,14 @@ sched #( .slots_o(next_slots) ); -`define assert(signal, value) \ - if (signal !== value) begin \ - $error("%m: signal != value"); \ - end +slot_t[1:0] first_check = {76'b0, + {{`rn(2), `alu(0)}, {`rn(3), `alu(0)}, {`alu(0), `rn(1)}, 8'h1, 20'h123} + }; -slot_t[1:0] first_check = {68'b0, {R2, ALU0}, {R3, ALU0}, {ALU0, R1}, 20'h123}; slot_t[1:0] second_check = { - {{R2, ALU0}, {R1, ALU0}, {ALU0, R5}, 20'h789}, - {{R2, ALU1}, {R1, ALU1}, {ALU1, R4}, 20'h456} - }; + {{`rn(2), `alu(0)}, {`rn(1), `alu(0)}, {`alu(0), `rn(5)}, 8'h3, 20'h789}, + {{`rn(2), `alu(1)}, {`rn(1), `alu(1)}, {`alu(1), `rn(4)}, 8'h2, 20'h456} + }; initial begin $dumpfile("sched_tb.vcd"); @@ -105,12 +49,12 @@ initial begin * add r4, r2, r1 add r5, r2, r1 */ prev_que = { - /* src2, src1, out, op, apparently. Have to get used to - * systemverilog's way of laying out bits, huh. */ - {{R2, ALU0}, {R1, ALU0}, {ALU0, R5}, 20'h789}, - {{R2, ALU1}, {R1, ALU1}, {ALU1, R4}, 20'h456}, - {{R2, ALU0}, {R3, ALU0}, {ALU0, R1}, 20'h123} - /* also, 'reverse' order, first instruction at bottom */ + /* src2, src1, out, op, apparently. Have to get used to + * systemverilog's way of laying out bits, huh. */ + {{`rn(2), `alu(0)}, {`rn(1), `alu(0)}, {`alu(0), `rn(5)}, 8'h3, 20'h789}, + {{`rn(2), `alu(1)}, {`rn(1), `alu(1)}, {`alu(1), `rn(4)}, 8'h2, 20'h456}, + {{`rn(2), `alu(0)}, {`rn(3), `alu(0)}, {`alu(0), `rn(1)}, 8'h1, 20'h123} + /* also, 'reverse' order, first instruction at bottom */ }; prev_slots = '0; @@ -118,7 +62,7 @@ initial begin #10 assert (next_slots == first_check) - else $error("\nwanted:\t%h", first_check, "\ngot:%h\t", next_slots); + else $error("\nwanted:\t%h", first_check, "\ngot:\t%h", next_slots); /* pretend all operations finished */ prev_slots = '0; |