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`include "common.svh"
module sched_tb;
typedef struct packed {
mov_t[1:0] in;
mov_t[0:0] out;
op_t op;
imm_t imm;
} slot_t;
slot_t[1:0] prev_slots;
slot_t[1:0] next_slots;
insn_t[2:0] prev_que;
insn_t[2:0] next_que;
sched #(
.QUE_DEPTH(3),
.SLOT_COUNT(2),
.SLOT_DEPTH(1),
.slot_t(slot_t)
) sched (
.que_i(prev_que),
.que_o(next_que),
.slots_i(prev_slots),
.slots_o(next_slots)
);
slot_t[1:0] first_check = {76'b0,
{{`rn(2), `alu(0)}, {`rn(3), `alu(0)}, {`alu(0), `rn(1)}, 8'h1, 20'h123}
};
slot_t[1:0] second_check = {
{{`rn(2), `alu(0)}, {`rn(1), `alu(0)}, {`alu(0), `rn(5)}, 8'h3, 20'h789},
{{`rn(2), `alu(1)}, {`rn(1), `alu(1)}, {`alu(1), `rn(4)}, 8'h2, 20'h456}
};
initial begin
$dumpfile("sched_tb.vcd");
$dumpvars();
/* pretend we've queued something like
* add r1, r2, r3
* add r4, r2, r1
* add r5, r2, r1
*
* should end up with something like
* add r1, r2, r3 noop
* add r4, r2, r1 add r5, r2, r1
*/
prev_que = {
/* src2, src1, out, op, apparently. Have to get used to
* systemverilog's way of laying out bits, huh. */
{{`rn(2), `alu(0)}, {`rn(1), `alu(0)}, {`alu(0), `rn(5)}, 8'h3, 20'h789},
{{`rn(2), `alu(1)}, {`rn(1), `alu(1)}, {`alu(1), `rn(4)}, 8'h2, 20'h456},
{{`rn(2), `alu(0)}, {`rn(3), `alu(0)}, {`alu(0), `rn(1)}, 8'h1, 20'h123}
/* also, 'reverse' order, first instruction at bottom */
};
prev_slots = '0;
#10
assert (next_slots == first_check)
else $error("\nwanted:\t%h", first_check, "\ngot:\t%h", next_slots);
/* pretend all operations finished */
prev_slots = '0;
prev_que = next_que;
#10
assert (next_slots == second_check)
else $error("\nwanted:\t%h", second_check, "\ngot:\t%h", next_slots);
#10 $finish;
end
endmodule
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