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| author | Kimplul <kimi.h.kuparinen@gmail.com> | 2022-04-10 15:39:41 +0300 |
|---|---|---|
| committer | Kimplul <kimi.h.kuparinen@gmail.com> | 2022-04-10 15:42:04 +0300 |
| commit | 8aa17b12f29536ea9c8b6ca22c7f153e8d90fa3b (patch) | |
| tree | e7dba9b6b9cdcd1d04cba639c8f76e9685ac549f /arch/riscv64/include/csr.h | |
| parent | 4760462d9b3bf2aba8664c57be85f4adbfa164a2 (diff) | |
| download | kmi-8aa17b12f29536ea9c8b6ca22c7f153e8d90fa3b.tar.gz kmi-8aa17b12f29536ea9c8b6ca22c7f153e8d90fa3b.zip | |
add clang format and run it
Diffstat (limited to 'arch/riscv64/include/csr.h')
| -rw-r--r-- | arch/riscv64/include/csr.h | 69 |
1 files changed, 34 insertions, 35 deletions
diff --git a/arch/riscv64/include/csr.h b/arch/riscv64/include/csr.h index 43c365b..7f9fc1f 100644 --- a/arch/riscv64/include/csr.h +++ b/arch/riscv64/include/csr.h @@ -3,43 +3,42 @@ #include <apos/utils.h> -#define SATP_MODE_Sv32 0x80000000 -#define SATP_MODE_Sv39 0x8000000000000000 -#define SATP_MODE_Sv48 0x9000000000000000 - +#define SATP_MODE_Sv32 0x80000000 +#define SATP_MODE_Sv39 0x8000000000000000 +#define SATP_MODE_Sv48 0x9000000000000000 /* supervisor CSR registers */ -#define CSR_SSTATUS 0x100 -#define CSR_SIE 0x104 -#define CSR_STVEC 0x105 -#define CSR_SCOUNTEREN 0x106 +#define CSR_SSTATUS 0x100 +#define CSR_SIE 0x104 +#define CSR_STVEC 0x105 +#define CSR_SCOUNTEREN 0x106 -#define CSR_SENVCFG 0x10A +#define CSR_SENVCFG 0x10A -#define CSR_SSCRATCH 0x140 -#define CSR_SEPC 0x141 -#define CSR_SCAUSE 0x142 -#define CSR_STVAL 0x143 -#define CSR_SIP 0x144 +#define CSR_SSCRATCH 0x140 +#define CSR_SEPC 0x141 +#define CSR_SCAUSE 0x142 +#define CSR_STVAL 0x143 +#define CSR_SIP 0x144 -#define CSR_SATP 0x180 +#define CSR_SATP 0x180 -#define CSR_SCONTEXT 0x5A8 +#define CSR_SCONTEXT 0x5A8 /* Exception causes */ -#define EXC_INST_MISALIGNED 0 -#define EXC_INST_ACCESS 1 -#define EXC_BREAKPOINT 3 -#define EXC_LOAD_ACCESS 5 -#define EXC_STORE_ACCESS 7 -#define EXC_SYSCALL 8 -#define EXC_INST_PAGE_FAULT 12 -#define EXC_LOAD_PAGE_FAULT 13 -#define EXC_STORE_PAGE_FAULT 15 +#define EXC_INST_MISALIGNED 0 +#define EXC_INST_ACCESS 1 +#define EXC_BREAKPOINT 3 +#define EXC_LOAD_ACCESS 5 +#define EXC_STORE_ACCESS 7 +#define EXC_SYSCALL 8 +#define EXC_INST_PAGE_FAULT 12 +#define EXC_LOAD_PAGE_FAULT 13 +#define EXC_STORE_PAGE_FAULT 15 /* status CSR bits */ -#define SSTATUS_SUM (1 << 18) -#define SSTATUS_SPP (1 << 8) +#define SSTATUS_SUM (1 << 18) +#define SSTATUS_SPP (1 << 8) /* directly lifted from Linux:/arch/riscv/include/asm/asm.h:9-13 */ #if defined(__ASSEMBLY__) @@ -48,16 +47,16 @@ #define __ASM_STR(x) #x #endif -#define csr_read(csr, res)\ - __asm__ volatile ("csrr %0, " __ASM_STR(csr) : "=r" (res) : : "memory") +#define csr_read(csr, res) \ + __asm__ volatile("csrr %0, " __ASM_STR(csr) : "=r"(res) : : "memory") -#define csr_write(csr, val)\ - __asm__ volatile ("csrw " __ASM_STR(csr) ", %0" : : "r" (val) : "memory") +#define csr_write(csr, val) \ + __asm__ volatile("csrw " __ASM_STR(csr) ", %0" : : "r"(val) : "memory") -#define csr_set(csr, val)\ - __asm__ volatile ("csrs " __ASM_STR(csr) ", %0" : : "r" (val) : "memory") +#define csr_set(csr, val) \ + __asm__ volatile("csrs " __ASM_STR(csr) ", %0" : : "r"(val) : "memory") -#define csr_clear(csr, val)\ - __asm__ volatile ("csrc " __ASM_STR(csr) ", %0" : : "r" (val) : "memory") +#define csr_clear(csr, val) \ + __asm__ volatile("csrc " __ASM_STR(csr) ", %0" : : "r"(val) : "memory") #endif /* APOS_CSR_H */ |