3 files changed, 180 insertions, 0 deletions
diff --git a/tests/simt_cache/sim.c b/tests/simt_cache/sim.c
new file mode 100644
index 0000000..780ef80
--- /dev/null
+++ b/tests/simt_cache/sim.c
@@ -0,0 +1,102 @@
+#include <assert.h>
+
+#include <gran/root.h>
+#include <gran/mem/simple_mem.h>
+#include <gran/bus/simple_bus.h>
+#include <gran/uart/simple_uart.h>
+#include <gran/mesh/node1d.h>
+#include <gran/cpu/riscv/simple_riscv64.h>
+#include <gran/cache/simt_cache.h>
+
+#include "../build/tests/simt_cache/test.inc"
+
+static stat build_simt(struct clock_domain *clk, uint16_t clusters, uint16_t lanes)
+{
+	struct component **mesh = calloc(clusters + 1, sizeof(struct component *));
+	assert(mesh);
+
+	for (int i = 1; i < clusters + 1; ++i) {
+		struct component *node = create_mesh_node1d(i, 3);
+		clock_domain_add(clk, node);
+		mesh[i] = node;
+
+		struct component *mem = create_simple_mem(4096);
+		init_simple_mem(mem, 0,
+				build_tests_simt_cache_test_inc_bin_len,
+				build_tests_simt_cache_test_inc_bin);
+
+		clock_domain_add(clk, mem);
+
+		uint64_t icache_rcv = mesh1d_addr(i, 0, 0);
+		struct component *icache = create_simt_cache(icache_rcv, lanes, node);
+		clock_domain_add(clk, icache);
+
+		uint64_t dcache_rcv = mesh1d_addr(i, 1, 0);
+		struct component *dcache = create_simt_cache(dcache_rcv, lanes, node);
+		clock_domain_add(clk, dcache);
+
+		for (int j = 0; j < lanes; ++j) {
+			struct component *rv64 = create_simple_riscv64(
+					(uint64_t)j << 32,
+					mesh1d_addr(i, 2, 0),
+					icache,
+					dcache
+			);
+
+			simple_riscv64_set_reg(rv64, 10, i); /* a0 */
+			simple_riscv64_set_reg(rv64, 11, j); /* a1 */
+			simple_riscv64_set_reg(rv64, 12, clusters); /* a2 */
+			simple_riscv64_set_reg(rv64, 13, lanes); /* a3 */
+			clock_domain_add(clk, rv64);
+
+			simt_cache_connect_lane(icache, j, rv64);
+			simt_cache_connect_lane(dcache, j, rv64);
+		}
+
+		mesh_node1d_connect(node, icache, 0);
+		mesh_node1d_connect(node, dcache, 1);
+		mesh_node1d_connect(node, mem, 2);
+	}
+
+	/* extra I/O node */
+	struct component *node = create_mesh_node1d(0, 2);
+	clock_domain_add(clk, node);
+	mesh[0] = node;
+
+	struct component *uart = create_simple_uart();
+	clock_domain_add(clk, uart);
+	mesh_node1d_connect(node, uart, 0);
+
+	struct component *mem = create_simple_mem(4096);
+	clock_domain_add(clk, mem);
+	mesh_node1d_connect(node, mem, 1);
+
+	for (int i = 0; i < clusters + 1; ++i) {
+		if (i - 1 >= 0)
+			mesh_node1d_connect_south(mesh[i], mesh[i - 1]);
+
+		if (i + 1 < clusters + 1)
+			mesh_node1d_connect_north(mesh[i], mesh[i + 1]);
+	}
+
+	free(mesh);
+	return OK;
+}
+
+int main()
+{
+	struct clock_domain *clk = create_clock_domain(NS(1));
+
+	/* one cluster with four cores + mem for each core (should
+	 * instructions be fetched from cluster local mem?) */
+	stat r = build_simt(clk, 8, 8);
+	assert(r == OK);
+
+	struct gran_root *root = create_root();
+	root_add_clock(root, clk);
+
+	r = root_run(root);
+	assert(r == OK);
+
+	destroy_root(root);
+}
diff --git a/tests/simt_cache/source.mk b/tests/simt_cache/source.mk
new file mode 100644
index 0000000..c9b5877
--- /dev/null
+++ b/tests/simt_cache/source.mk
@@ -0,0 +1,11 @@
+SIMT_CACHE	:= tests/simt_cache
+SIMT_CACHE_SIM	:= $(SIMT_CACHE)/sim.c
+
+TESTS += $(SIMT_CACHE)/sim
+
+.PHONY: $(SIMT_CACHE)/sim
+$(SIMT_CACHE)/sim: $(SIMT_CACHE_SIM) libgran.a
+	mkdir -p build/$(SIMT_CACHE)
+	./scripts/gen-rv64-fw -d build -o $(SIMT_CACHE)/test.inc $(SIMT_CACHE)/test.c
+	$(COMPILE_TEST) $(SIMT_CACHE_SIM) libgran.a -o build/$@
+	./scripts/gen-report -d build $@
diff --git a/tests/simt_cache/test.c b/tests/simt_cache/test.c
new file mode 100644
index 0000000..df86774
--- /dev/null
+++ b/tests/simt_cache/test.c
@@ -0,0 +1,67 @@
+#include <stdint.h>
+
+__attribute__((always_inline))
+static inline uint64_t mesh1d_addr(uint16_t cluster, uint16_t elem,
+                                   uint32_t off)
+{
+	return ((uint64_t)cluster << 48) | ((uint64_t)elem << 32) | off;
+}
+
+__attribute__((always_inline))
+static inline void print_int8(volatile char *uart, unsigned x)
+{
+	char lo_nibble = (x >> 0) & 0xf;
+	char hi_nibble = (x >> 4) & 0xf;
+
+	*uart = hi_nibble < 10 ? hi_nibble + '0' : (hi_nibble - 10) + 'a';
+	*uart = lo_nibble < 10 ? lo_nibble + '0' : (lo_nibble - 10) + 'a';
+}
+
+__attribute__((always_inline))
+static inline void print_addr(volatile char *uart, unsigned x, unsigned y)
+{
+	*uart = '(';
+	print_int8(uart, x);
+	*uart = ',';
+	*uart = ' ';
+	print_int8(uart, y);
+	*uart = ')';
+	*uart = '\n';
+}
+
+__attribute__((always_inline))
+static inline uint64_t wrap(unsigned x, unsigned X)
+{
+	return x + 1 >= X ? 0 : x + 1;
+}
+
+__attribute__((always_inline))
+static inline uint64_t next_idx(unsigned x, unsigned y, unsigned X, unsigned Y)
+{
+	unsigned yi = wrap(y, Y);
+	unsigned xi = yi < y ? wrap(x, X) : x;
+
+	return mesh1d_addr(xi, yi, 0);
+}
+
+void _start(unsigned x, unsigned y, unsigned X, unsigned Y)
+{
+	volatile char *uart = (char *)mesh1d_addr(0, 0, 0);
+	volatile uint64_t *control = (uint64_t *)mesh1d_addr(0, 1, 0);
+
+	if (x == 1 && y == 0) {
+		goto do_work;
+	} else {
+		while (*control != mesh1d_addr(x, y, 0)) {}
+	}
+
+do_work:
+	print_addr(uart, x, y);
+	*control = next_idx(x, y, X, Y);
+
+	if (x == X - 1 && y == Y - 1)
+		asm ("ebreak");
+
+	/* otherwise just loop */
+	while (1) {}
+}