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authorKimplul <kimi.h.kuparinen@gmail.com>2025-12-24 00:38:37 +0200
committerKimplul <kimi.h.kuparinen@gmail.com>2025-12-24 00:49:21 +0200
commitead834152ffec8559eb37e9887d215fcf60338a2 (patch)
tree0186a224b41db052788822602b33b4d7f895fda3 /tests/simt_cache/source.mk
parent1870c54a43194632a45b2c945bc53b329acb4b1e (diff)
downloadgran-master.tar.gz
gran-master.zip
implement interconnect for simt cacheHEADmaster
+ Actual cache still missing, lol + Initial performance numbers aren't too promising compared to simt_riscv64 or even simple_mesh1d, but there's a somewhat increased latency due to registering inputs and the shared req logic which can likely be improved. Will have to dig into this a bit further
Diffstat (limited to 'tests/simt_cache/source.mk')
-rw-r--r--tests/simt_cache/source.mk11
1 files changed, 11 insertions, 0 deletions
diff --git a/tests/simt_cache/source.mk b/tests/simt_cache/source.mk
new file mode 100644
index 0000000..c9b5877
--- /dev/null
+++ b/tests/simt_cache/source.mk
@@ -0,0 +1,11 @@
+SIMT_CACHE := tests/simt_cache
+SIMT_CACHE_SIM := $(SIMT_CACHE)/sim.c
+
+TESTS += $(SIMT_CACHE)/sim
+
+.PHONY: $(SIMT_CACHE)/sim
+$(SIMT_CACHE)/sim: $(SIMT_CACHE_SIM) libgran.a
+ mkdir -p build/$(SIMT_CACHE)
+ ./scripts/gen-rv64-fw -d build -o $(SIMT_CACHE)/test.inc $(SIMT_CACHE)/test.c
+ $(COMPILE_TEST) $(SIMT_CACHE_SIM) libgran.a -o build/$@
+ ./scripts/gen-report -d build $@