From ead834152ffec8559eb37e9887d215fcf60338a2 Mon Sep 17 00:00:00 2001 From: Kimplul Date: Wed, 24 Dec 2025 00:38:37 +0200 Subject: implement interconnect for simt cache + Actual cache still missing, lol + Initial performance numbers aren't too promising compared to simt_riscv64 or even simple_mesh1d, but there's a somewhat increased latency due to registering inputs and the shared req logic which can likely be improved. Will have to dig into this a bit further --- tests/simt_cache/source.mk | 11 +++++++++++ 1 file changed, 11 insertions(+) create mode 100644 tests/simt_cache/source.mk (limited to 'tests/simt_cache/source.mk') diff --git a/tests/simt_cache/source.mk b/tests/simt_cache/source.mk new file mode 100644 index 0000000..c9b5877 --- /dev/null +++ b/tests/simt_cache/source.mk @@ -0,0 +1,11 @@ +SIMT_CACHE := tests/simt_cache +SIMT_CACHE_SIM := $(SIMT_CACHE)/sim.c + +TESTS += $(SIMT_CACHE)/sim + +.PHONY: $(SIMT_CACHE)/sim +$(SIMT_CACHE)/sim: $(SIMT_CACHE_SIM) libgran.a + mkdir -p build/$(SIMT_CACHE) + ./scripts/gen-rv64-fw -d build -o $(SIMT_CACHE)/test.inc $(SIMT_CACHE)/test.c + $(COMPILE_TEST) $(SIMT_CACHE_SIM) libgran.a -o build/$@ + ./scripts/gen-report -d build $@ -- cgit v1.3