1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
|
`include "common.svh"
`default_nettype none
module ttarv32 #(
parameter SLOT_COUNT,
parameter ALU_COUNT
)(
input clk_i,
input rst_ni,
input rv_t[SLOT_COUNT-1:0] rv_i,
output xlen_t pc_o
);
typedef struct packed {
mov_t[1:0] in;
mov_t out;
op_t op;
imm_t imm;
} slot_t;
insn_t[SLOT_COUNT-1:0] rv_que;
insn_t[SLOT_COUNT-1:0] prev_que_r;
insn_t[SLOT_COUNT-1:0] next_que;
slot_t[SLOT_COUNT-1:0] prev_slots_r;
slot_t[SLOT_COUNT-1:0] next_slots;
xlen_t pc_r;
rv2insn #(
.QUE_DEPTH(SLOT_COUNT),
.ALU_COUNT(ALU_COUNT)
) rv2insn (
.clk_i(clk_i),
.rst_ni(rst_ni),
.pc_i(pc_r),
.rv_i(rv_i),
.que_o(rv_que)
);
function automatic insn_t[SLOT_COUNT-1:0] merge(insn_t[SLOT_COUNT-1:0] prev_que, insn_t[SLOT_COUNT-1:0] decoded, bit[$clog2(SLOT_COUNT)-1:0] shift);
return prev_que | (decoded << (shift * $bits(insn_t)));
endfunction
bit[$clog2(SLOT_COUNT)-1:0] shift_r, shift;
insn_t[SLOT_COUNT-1:0] merged_que;
assign merged_que = merge(prev_que_r, rv_que, shift_r);
sched #(
.QUE_DEPTH(SLOT_COUNT),
.SLOT_COUNT(SLOT_COUNT),
.slot_t(slot_t)
) sched (
.clk_i(clk_i),
.rst_ni(rst_ni),
.que_i(merged_que),
.que_o(next_que),
.slots_i(prev_slots_r),
.slots_o(next_slots),
.shift_o(shift)
);
always_ff @(posedge clk_i or negedge rst_ni) begin
if (!rst_ni) begin
prev_slots_r <= 0;
prev_que_r <= 0;
shift_r <= 0;
pc_r <= 0;
pc_o <= 0;
end else begin
prev_slots_r <= next_slots;
prev_que_r <= next_que;
shift_r <= shift;
pc_o <= pc_r + xlen_t'(shift);
pc_r <= pc_o;
end
end
endmodule
|
