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`include "common.svh"
module sched
#(
parameter QUE_DEPTH,
parameter SLOT_COUNT,
parameter SLOT_DEPTH,
type port_t,
type mov_t,
type insn_t,
type slot_t
)(
input insn_t[QUE_DEPTH-1:0] que_i,
output insn_t[QUE_DEPTH-1:0] que_o,
input slot_t[SLOT_COUNT-1:0] slots_i,
output slot_t[SLOT_COUNT-1:0] slots_o
);
/* check_* don't always use whole signal they're given, so I think it's best to
* just silence this */
/* verilator lint_off UNUSEDSIGNAL */
function automatic insn_t[QUE_DEPTH-1:0] next_insn(insn_t[QUE_DEPTH-1:0] que);
return que >> $bits(insn_t);
endfunction
/* check if a write is to the same destination port */
function automatic logic check_dst(mov_t d1, mov_t[SLOT_DEPTH-1:0] d2);
logic[SLOT_DEPTH-1:0] dep = '0;
for (int i = 0; i < SLOT_DEPTH; ++i) begin
dep[i] = d1.dst != `NOP & d1.dst == d2[i].dst;
end
return dep != 0;
endfunction
/* check if any read is from an output port that's not free */
function automatic logic check_overlap(mov_t d1, mov_t[SLOT_DEPTH-1:0] d2);
logic[SLOT_DEPTH-1:0] dep = '0;
for (int i = 0; i < SLOT_DEPTH; ++i) begin
dep[i] = d1.src != `NOP & d1.src == d2[i].dst;
end
return dep != 0;
endfunction
/* check if instruction depends on any existing slots */
function automatic logic depends(insn_t i, slot_t[SLOT_COUNT-1:0] slots);
logic[SLOT_COUNT-1:0] dep = '0;
for (int ii = 0; ii < SLOT_COUNT; ++ii) begin
logic same_dst = check_dst(i.out, slots[ii].out);
logic overlap1 = check_overlap(i.in[0], slots[ii].out);
logic overlap2 = check_overlap(i.in[1], slots[ii].out);
logic same_src1 = i.in[0].dst != `NOP
& i.in[0].dst == slots[ii].in[0].dst;
/* op must have trigger so don't need to check against NOP */
logic same_src2 = i.in[1].dst == slots[ii].in[1].dst;
dep[ii] = same_dst | overlap1 | overlap2 | same_src1 | same_src2;
end
return dep != 0;
endfunction
function automatic logic is_noop(mov_t m);
return m.src == `NOP && m.dst == `NOP;
endfunction
function automatic mov_t[SLOT_DEPTH-1:0] place_out(int i, logic placed,
mov_t o, mov_t[SLOT_DEPTH-1:0] out);
if (i < SLOT_DEPTH) begin
logic ok = !placed & is_noop(out[i]);
out[i] = ok ? o : out[i];
return place_out(i + 1, ok ? 1 : placed, o, out);
end else begin
return out;
end
endfunction
/* place instruction into slot */
function automatic slot_t place(insn_t i, slot_t src);
slot_t slot;
slot.op = i.op;
slot.in = i.in;
slot.out = place_out(0, 0, i.out, src.out);
return slot;
endfunction
typedef struct packed {
insn_t[QUE_DEPTH-1:0] que;
slot_t[SLOT_COUNT-1:0] slots;
} stages_out_t;
function automatic stages_out_t stages(int i,
insn_t[QUE_DEPTH-1:0] que, slot_t[SLOT_COUNT-1:0] slots);
if (i < SLOT_COUNT) begin
logic ok = !depends(que[0], slots);
slots[i] = ok ? place(que[0], slots[i]) : slots[i];
return stages(i + 1, ok ? next_insn(que) : que, slots);
end else begin
return {que, slots};
end
endfunction
always_comb begin
stages_out_t out = stages(0, que_i, slots_i);
que_o = out.que;
slots_o = out.slots;
end
endmodule
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