index
:
ttarv32
master
Getting familiar with SystemVerilog by writing an in-order multi-issue rv32 core
kimi.h.kuparinen+ttarv32@gmail.com
summary
refs
log
tree
commit
diff
log msg
author
committer
range
path:
root
/
src
Mode
Name
Size
-rw-r--r--
common.svh
2015
log
plain
blame
-rw-r--r--
rv2insn.sv
2580
log
plain
blame
-rw-r--r--
sched.sv
3003
log
plain
blame
-rw-r--r--
ttarv32.sv
2047
log
plain
blame