ttarv32 - GOOFING OFF - Getting familiar with SystemVerilog by writing an in-order multi-issue rv32 core

Age	Commit message (Collapse)	Author
11 days	compile with verilator -WallHEAD master	Kimplul
	+ I also found out that iverilog does not agree with Verilator that the testbenches work (the ones that iverilog can compile, anyway). That's rather annoying, I'm not quite sure what the root cause is. Timing difference in when registers are evaluated versus clock edges or something along those lines?
2026-09-27	implement circular router	Kimplul
	+ Not great latency, but has a fairly high fmax and low resource usage on my FPGA, so go with this for now. Likely better suited for data path, unsure what I'll do for the control path.