compile with verilator -WallHEADmaster

+ I also found out that iverilog does not agree with Verilator that the
  testbenches work (the ones that iverilog can compile, anyway). That's
  rather annoying, I'm not quite sure what the root cause is. Timing
  difference in when registers are evaluated versus clock edges or
  something along those lines?

1 files changed, 4 insertions, 2 deletions

diff --git a/tb/router_tb.sv b/tb/router_tb.sv
index ba83568..10bcfdd 100644
--- a/tb/router_tb.sv
+++ b/tb/router_tb.sv
@@ -79,9 +79,11 @@ assign ready_i[0][0] = ready_o[1][1];
 
 
 initial begin :test
-	logic found = 0;
+	logic found;
 
-	$dumpfile("router_tb.vcd");
+	found = 0;
+
+	$dumpfile("router_tb.fst");
 	$dumpvars();
 
 	for (int i = 0; i < M; ++i)