| Age | Commit message (Expand) | Author |
|---|---|---|
| 11 days | compile with verilator -WallHEADmaster | Kimplul |
| 2026-09-27 | implement circular router | Kimplul |
| 2026-06-22 | add simple round-robin arbiter | Kimplul |
| 2025-02-16 | add some kind of toplevel | Kimplul |
| 2025-02-16 | add initial risc-v -> tta translation block | Kimplul |
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index : ttarv32 | |
| GOOFING OFF - Getting familiar with SystemVerilog by writing an in-order multi-issue rv32 core | kimi.h.kuparinen+ttarv32@gmail.com |
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