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+ I also found out that iverilog does not agree with Verilator that the
testbenches work (the ones that iverilog can compile, anyway). That's
rather annoying, I'm not quite sure what the root cause is. Timing
difference in when registers are evaluated versus clock edges or
something along those lines?
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+ Verilator does not check undefined values and unused wire warnings
only show up with -Wall (as warnings) so I just missed this
completely, hah. Surprised the testbench passed, I guess it's just not
quite up to snuff.
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+ Not great latency, but has a fairly high fmax and low resource usage
on my FPGA, so go with this for now. Likely better suited for data
path, unsure what I'll do for the control path.
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+ Had a higher fMax and smaller area compared to previous attempt,
at least when synthesized with OpenROAD
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+ Should check how well it synthesises with OpenROAD or something,
Vivado seemed to kind of choke on it and it was way slower/bigger than
I was expecting.
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+ Not fully functional, but good enough for now
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