fix missing connection in skid buffer

+ Verilator does not check undefined values and unused wire warnings
  only show up with -Wall (as warnings) so I just missed this
  completely, hah. Surprised the testbench passed, I guess it's just not
  quite up to snuff.

1 files changed, 6 insertions, 0 deletions

diff --git a/src/skid_buffer.sv b/src/skid_buffer.sv
index 3ea6d0d..0bb5617 100644
--- a/src/skid_buffer.sv
+++ b/src/skid_buffer.sv
@@ -37,6 +37,12 @@ if (!rstx_i)
 else if (b_fill)
 	b <= a;
 
+always_ff @(posedge clk_i or negedge rstx_i)
+if (!rstx_i)
+	b_full <= '0;
+else if (b_fill || b_drain)
+	b_full <= b_fill;
+
 /* fill A first, if upstream can't read A in time, place A into B and skid the
  * input into A until upstream can clean out B */
 assign a_fill  = valid_i &&  ready_o;