compile with verilator -WallHEADmaster

+ I also found out that iverilog does not agree with Verilator that the
  testbenches work (the ones that iverilog can compile, anyway). That's
  rather annoying, I'm not quite sure what the root cause is. Timing
  difference in when registers are evaluated versus clock edges or
  something along those lines?

1 files changed, 3 insertions, 3 deletions

diff --git a/tb/ttarv32_tb.sv b/tb/ttarv32_tb.sv
index 5b30f25..9ff089d 100644
--- a/tb/ttarv32_tb.sv
+++ b/tb/ttarv32_tb.sv
@@ -10,7 +10,7 @@ function automatic rv_t[3:0] unp2p(logic[7:0] in[4*4]);
 	return conversion;
 endfunction
 
-xlen_t pc;
+xlen_t unused_pc;
 logic[7:0] rv[4*4];
 
 logic clk;
@@ -23,11 +23,11 @@ ttarv32 #(
 	.clk_i(clk),
 	.rst_ni(rst_n),
 	.rv_i(unp2p(rv)),
-	.pc_o(pc)
+	.pc_o(unused_pc)
 );
 
 initial begin
-	$dumpfile("ttarv32_tb.vcd");
+	$dumpfile("ttarv32_tb.fst");
 	$dumpvars();
 	$readmemh("ttarv32.hex", rv);