simplift arbHEADmaster

+ Had a higher fMax and smaller area compared to previous attempt,
  at least when synthesized with OpenROAD

1 files changed, 6 insertions, 6 deletions

diff --git a/tb/arb_tb.sv b/tb/arb_tb.sv
index 909c5b2..53b9cb2 100644
--- a/tb/arb_tb.sv
+++ b/tb/arb_tb.sv
@@ -4,7 +4,7 @@ localparam WIDTH = 32;
 
 reg clk;
 reg rstx;
-logic[WIDTH-1:0] cand;
+logic[WIDTH-1:0] valid;
 logic[WIDTH-1:0] selected;
 
 arb #(
@@ -12,7 +12,7 @@ arb #(
 ) arb_i (
 	.clk(clk),
 	.rstx(rstx),
-	.cand(cand),
+	.valid(valid),
 	.selected(selected)
 );
 
@@ -33,12 +33,12 @@ initial begin
 
 	/* honestly, I'm a bit confused about this, if I try to make this be at
 	* a positive clock edge, the selected == 1 condition disappears because
-	* cand apparently triggers `selected` to be recalculated first, which
+	* valid apparently triggers `selected` to be recalculated first, which
 	* then is fed into `mask` which then re-triggers `selected` and causes
 	* it to 'skip' ahead to selected == 2. When looking at the waveforms,
 	* the next @(posedge clk) shows 2 while the assert passes. I guess the
 	* assert is run first in the time step...? */
-	cand = ~0;
+	valid = ~0;
 
 	@(posedge clk);
 	assert (selected == 1)
@@ -54,13 +54,13 @@ initial begin
 	else $error("expected 4, got ", selected);
 
 	/* skip next index */
-	cand = '0;
+	valid = '0;
 
 	@(posedge clk);
 	assert (selected == 0)
 	else $error("expected 0, got ", selected);
 
-	cand = ~8;
+	valid = ~8;
 
 	@(posedge clk);
 	assert (selected == 16)