compile with verilator -WallHEADmaster

+ I also found out that iverilog does not agree with Verilator that the
  testbenches work (the ones that iverilog can compile, anyway). That's
  rather annoying, I'm not quite sure what the root cause is. Timing
  difference in when registers are evaluated versus clock edges or
  something along those lines?

1 files changed, 5 insertions, 4 deletions

diff --git a/src/router.sv b/src/router.sv
index b496ab9..2783b69 100644
--- a/src/router.sv
+++ b/src/router.sv
@@ -45,7 +45,6 @@ module router #(
 );
 
 localparam NW = $bits(addr_i[0].dst.node);
-localparam DW = $bits(addr_i[0].dst.dev);
 
 typedef struct packed {
 	logic alive;
@@ -93,8 +92,8 @@ for (genvar i = 0; i < N + 2; ++i) begin :skidbuffers
 	);
 end
 
-for (genvar i = 0; i < N + 2; ++i)
-always_comb begin :gen_ring_knot
+for (genvar i = 0; i < N + 2; ++i) begin :gen_ring_knot
+always_comb begin
 	/* default values */
 	handle[i] = ring_d[i];
 	send[i]   = 1'b0;
@@ -151,10 +150,12 @@ always_comb begin :gen_ring_knot
 	 * the ring */
 	ring_q[(i + 1) % (N + 2)] = recv[i] ? insert[i] : handle[i];
 end
+end
 
-for (genvar i = 0; i < N + 2; ++i)
+for (genvar i = 0; i < N + 2; ++i) begin :gen_ring_ff
 always_ff @(posedge clk_i or negedge rstx_i)
 if (!rstx_i) ring_d[i] <= '0;
 else         ring_d[i] <= ring_q[i];
+end
 
 endmodule // router