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| author | Kimplul <kimi.h.kuparinen@gmail.com> | 2026-11-03 21:32:31 +0200 |
|---|---|---|
| committer | Kimplul <kimi.h.kuparinen@gmail.com> | 2026-11-03 21:32:31 +0200 |
| commit | 0c6297a079795927ea2c85e884aaa57cd5a6ca30 (patch) | |
| tree | b2e98455365f9d0534e92bf3a7a6e4120a0eae8e /src/common.svh | |
| parent | b9afe2d4c22e35f2d2e65d67c07b300ba3f7ccb3 (diff) | |
| download | ttarv32-0c6297a079795927ea2c85e884aaa57cd5a6ca30.tar.gz ttarv32-0c6297a079795927ea2c85e884aaa57cd5a6ca30.zip | |
+ I also found out that iverilog does not agree with Verilator that the
testbenches work (the ones that iverilog can compile, anyway). That's
rather annoying, I'm not quite sure what the root cause is. Timing
difference in when registers are evaluated versus clock edges or
something along those lines?
Diffstat (limited to 'src/common.svh')
0 files changed, 0 insertions, 0 deletions