blob: a85ae6fc8c5c2a7fea0e43d42799cc731c5c3ade (
plain) (
blame)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
|
/**
* @file proc.c
* riscv64 implementation of arch-specific process handling.
*/
#include <apos/tcb.h>
#include <apos/elf.h>
#include "regs.h"
#include "csr.h"
/** \todo actually map fdt into the target address space */
stat_t run_init(struct tcb *t, void *fdt)
{
csr_write(CSR_SSCRATCH, t);
__asm__ volatile ("mv sp, %0\n" : : "r" (t->thread_stack_top) : "memory");
__asm__ volatile ("mv a0, %0\n" : : "r" (fdt) : );
__asm__ volatile ("sret\n" ::: "memory");
/* we should never reach this */
return ERR_ADDR;
}
stat_t set_return(vm_t v)
{
csr_write(CSR_SEPC, v);
return OK;
}
stat_t set_ipc(struct tcb *t, id_t pid, id_t tid)
{
struct riscv_regs *r = (struct riscv_regs *)(--t);
r->a2 = (long)pid;
r->a3 = (long)tid;
return OK;
}
stat_t set_thread(struct tcb *t)
{
/* get location of registers in memory */
/** \todo check alignment, should be fine but just to be sure */
struct riscv_regs *r = (struct riscv_regs *)(--t);
/* insert important values into register slots */
r->sp = (long)t->thread_stack_top;
r->tp = (long)t->thread_storage;
return OK;
}
|
