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-rw-r--r--arch/riscv64/gen/asm-offsets.c2
-rw-r--r--arch/riscv64/include/csr.h8
-rw-r--r--arch/riscv64/include/regs.h2
-rw-r--r--arch/riscv64/init/init.c4
-rw-r--r--arch/riscv64/kernel/proc.c4
-rw-r--r--arch/riscv64/kernel/sbi.c25
-rw-r--r--arch/riscv64/kernel/vmem.c4
7 files changed, 25 insertions, 24 deletions
diff --git a/arch/riscv64/gen/asm-offsets.c b/arch/riscv64/gen/asm-offsets.c
index bbd1712..9d44ec6 100644
--- a/arch/riscv64/gen/asm-offsets.c
+++ b/arch/riscv64/gen/asm-offsets.c
@@ -9,7 +9,7 @@
/* largely based on linux */
#define DEFINE(sym, val) \
- __asm__ volatile("\n#-> " #sym " %0 " #val "\n" ::"i"(val))
+ __asm__ volatile ("\n#-> " #sym " %0 " #val "\n" : : "i" (val))
#define OFFSETOF(m, s) DEFINE(offsetof_##m, offsetof(s, m))
#define SIZEOF(n, s) DEFINE(sizeof_##n, sizeof(s))
diff --git a/arch/riscv64/include/csr.h b/arch/riscv64/include/csr.h
index 93bba2b..ade397c 100644
--- a/arch/riscv64/include/csr.h
+++ b/arch/riscv64/include/csr.h
@@ -55,15 +55,15 @@
#endif
#define csr_read(csr, res) \
- __asm__ volatile("csrr %0, " __ASM_STR(csr) : "=r"(res) : : "memory")
+ __asm__ volatile ("csrr %0, " __ASM_STR(csr) : "=r" (res) : : "memory")
#define csr_write(csr, val) \
- __asm__ volatile("csrw " __ASM_STR(csr) ", %0" : : "r"(val) : "memory")
+ __asm__ volatile ("csrw " __ASM_STR(csr) ", %0" : : "r" (val) : "memory")
#define csr_set(csr, val) \
- __asm__ volatile("csrs " __ASM_STR(csr) ", %0" : : "r"(val) : "memory")
+ __asm__ volatile ("csrs " __ASM_STR(csr) ", %0" : : "r" (val) : "memory")
#define csr_clear(csr, val) \
- __asm__ volatile("csrc " __ASM_STR(csr) ", %0" : : "r"(val) : "memory")
+ __asm__ volatile ("csrc " __ASM_STR(csr) ", %0" : : "r" (val) : "memory")
#endif /* APOS_CSR_H */
diff --git a/arch/riscv64/include/regs.h b/arch/riscv64/include/regs.h
index c785ea6..511934e 100644
--- a/arch/riscv64/include/regs.h
+++ b/arch/riscv64/include/regs.h
@@ -12,7 +12,7 @@
struct riscv_regs {
long ra, sp, gp, tp, t0, t1, t2, s0, s1, a0, a1, a2, a3, a4, a5, a6, a7,
- s2, s3, s4, s5, s6, s7, s8, s9, s10, s11, t3, t4, t5, t6;
+ s2, s3, s4, s5, s6, s7, s8, s9, s10, s11, t3, t4, t5, t6;
};
#endif /* APOS_RISCV_REGS_H */
diff --git a/arch/riscv64/init/init.c b/arch/riscv64/init/init.c
index 5984d3c..c76c81c 100644
--- a/arch/riscv64/init/init.c
+++ b/arch/riscv64/init/init.c
@@ -56,9 +56,9 @@ void move_kernel()
#define __va_reg(reg) \
{ \
vm_t reg = 0; \
- __asm__("mv %0, " QUOTE(reg) : "=r"(reg)::); \
+ __asm__ ("mv %0, " QUOTE(reg) : "=r" (reg)::); \
reg = (vm_t)__va(reg); \
- __asm__("mv " QUOTE(reg) ", %0" ::"rK"(reg) :); \
+ __asm__ ("mv " QUOTE(reg) ", %0" ::"rK" (reg) :); \
}
void init(void *fdt)
diff --git a/arch/riscv64/kernel/proc.c b/arch/riscv64/kernel/proc.c
index 51a4ab3..b378a72 100644
--- a/arch/riscv64/kernel/proc.c
+++ b/arch/riscv64/kernel/proc.c
@@ -12,8 +12,8 @@ stat_t jump_to_userspace(struct tcb *t, int argc, char **argv)
{
csr_write(CSR_SEPC, t->entry);
csr_write(CSR_SSCRATCH, t);
- __asm__ volatile("mv sp, %0\n" ::"r"(t->proc_stack_top) : "memory");
- __asm__ volatile("sret\n" ::: "memory");
+ __asm__ volatile ("mv sp, %0\n" : : "r" (t->proc_stack_top) : "memory");
+ __asm__ volatile ("sret\n" ::: "memory");
/* we should never reach this */
return ERR_ADDR;
}
diff --git a/arch/riscv64/kernel/sbi.c b/arch/riscv64/kernel/sbi.c
index feadd8d..6a417d8 100644
--- a/arch/riscv64/kernel/sbi.c
+++ b/arch/riscv64/kernel/sbi.c
@@ -12,19 +12,20 @@ struct sbiret sbi_ecall(int ext, int fid, unsigned long arg0,
{
struct sbiret ret;
- register uintptr_t a0 __asm__("a0") = (uintptr_t)(arg0);
- register uintptr_t a1 __asm__("a1") = (uintptr_t)(arg1);
- register uintptr_t a2 __asm__("a2") = (uintptr_t)(arg2);
- register uintptr_t a3 __asm__("a3") = (uintptr_t)(arg3);
- register uintptr_t a4 __asm__("a4") = (uintptr_t)(arg4);
- register uintptr_t a5 __asm__("a5") = (uintptr_t)(arg5);
- register uintptr_t a6 __asm__("a6") = (uintptr_t)(fid);
- register uintptr_t a7 __asm__("a7") = (uintptr_t)(ext);
+ register uintptr_t a0 __asm__ ("a0") = (uintptr_t)(arg0);
+ register uintptr_t a1 __asm__ ("a1") = (uintptr_t)(arg1);
+ register uintptr_t a2 __asm__ ("a2") = (uintptr_t)(arg2);
+ register uintptr_t a3 __asm__ ("a3") = (uintptr_t)(arg3);
+ register uintptr_t a4 __asm__ ("a4") = (uintptr_t)(arg4);
+ register uintptr_t a5 __asm__ ("a5") = (uintptr_t)(arg5);
+ register uintptr_t a6 __asm__ ("a6") = (uintptr_t)(fid);
+ register uintptr_t a7 __asm__ ("a7") = (uintptr_t)(ext);
- __asm__ volatile("ecall"
- : "+r"(a0), "+r"(a1)
- : "r"(a2), "r"(a3), "r"(a4), "r"(a5), "r"(a6), "r"(a7)
- : "memory");
+ __asm__ volatile ("ecall"
+ : "+r" (a0), "+r" (a1)
+ : "r" (a2), "r" (a3), "r" (a4), "r" (a5), "r" (a6),
+ "r" (a7)
+ : "memory");
ret.error = a0;
ret.value = a1;
diff --git a/arch/riscv64/kernel/vmem.c b/arch/riscv64/kernel/vmem.c
index 56b04f3..d7c823b 100644
--- a/arch/riscv64/kernel/vmem.c
+++ b/arch/riscv64/kernel/vmem.c
@@ -142,12 +142,12 @@ stat_t unmap_vpage(struct vmem *branch, vm_t vaddr)
void flush_tlb()
{
- __asm__ volatile("sfence.vma %0\n" ::"r"(cpu_id()) : "memory");
+ __asm__ volatile ("sfence.vma %0\n" : : "r" (cpu_id()) : "memory");
}
void flush_tlb_all()
{
- __asm__ volatile("sfence.vma\n" ::: "memory");
+ __asm__ volatile ("sfence.vma\n" ::: "memory");
}
static void __start_vmem(struct vmem *branch, enum mm_mode m)