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| author | Kimplul <kimi.h.kuparinen@gmail.com> | 2022-05-29 11:23:29 +0300 |
|---|---|---|
| committer | Kimplul <kimi.h.kuparinen@gmail.com> | 2022-05-29 11:23:29 +0300 |
| commit | e148f38dc937c34b222ba8df8612b3fa2b6bc349 (patch) | |
| tree | c51f045c6632b2073cb0e3183bd9d3b559ccd228 /arch/riscv64/kernel | |
| parent | 360c18fcbe228220e5c9799fb30b2032982c06cf (diff) | |
| download | kmi-e148f38dc937c34b222ba8df8612b3fa2b6bc349.tar.gz kmi-e148f38dc937c34b222ba8df8612b3fa2b6bc349.zip | |
modify formatting rules
Diffstat (limited to 'arch/riscv64/kernel')
| -rw-r--r-- | arch/riscv64/kernel/csr.h | 8 | ||||
| -rw-r--r-- | arch/riscv64/kernel/regs.h | 2 |
2 files changed, 5 insertions, 5 deletions
diff --git a/arch/riscv64/kernel/csr.h b/arch/riscv64/kernel/csr.h index ade397c..9cb5799 100644 --- a/arch/riscv64/kernel/csr.h +++ b/arch/riscv64/kernel/csr.h @@ -54,16 +54,16 @@ #define __ASM_STR(x) #x #endif -#define csr_read(csr, res) \ +#define csr_read(csr, res) \ __asm__ volatile ("csrr %0, " __ASM_STR(csr) : "=r" (res) : : "memory") -#define csr_write(csr, val) \ +#define csr_write(csr, val) \ __asm__ volatile ("csrw " __ASM_STR(csr) ", %0" : : "r" (val) : "memory") -#define csr_set(csr, val) \ +#define csr_set(csr, val) \ __asm__ volatile ("csrs " __ASM_STR(csr) ", %0" : : "r" (val) : "memory") -#define csr_clear(csr, val) \ +#define csr_clear(csr, val) \ __asm__ volatile ("csrc " __ASM_STR(csr) ", %0" : : "r" (val) : "memory") #endif /* APOS_CSR_H */ diff --git a/arch/riscv64/kernel/regs.h b/arch/riscv64/kernel/regs.h index 97bb17e..f2bf336 100644 --- a/arch/riscv64/kernel/regs.h +++ b/arch/riscv64/kernel/regs.h @@ -12,7 +12,7 @@ struct riscv_regs { long ra, sp, gp, tp, t0, t1, t2, s0, s1, a0, a1, a2, a3, a4, a5, a6, a7, - s2, s3, s4, s5, s6, s7, s8, s9, s10, s11, t3, t4, t5, t6; + s2, s3, s4, s5, s6, s7, s8, s9, s10, s11, t3, t4, t5, t6; }; #endif /* APOS_RISCV_REGS_H */ |