continue documentation efforts

1 files changed, 66 insertions, 2 deletions

diff --git a/arch/riscv64/kernel/regs.h b/arch/riscv64/kernel/regs.h
index f2bf336..bda3c1d 100644
--- a/arch/riscv64/kernel/regs.h
+++ b/arch/riscv64/kernel/regs.h
@@ -10,9 +10,73 @@
  * @todo Implement sacing floating point, vector, etc. registers.
  */
 
+/**
+ * Structure containing registers that should always be saved.
+ * Essentially all base ISA registers.
+ */
 struct riscv_regs {
-	long ra, sp, gp, tp, t0, t1, t2, s0, s1, a0, a1, a2, a3, a4, a5, a6, a7,
-	        s2, s3, s4, s5, s6, s7, s8, s9, s10, s11, t3, t4, t5, t6;
+	/** Return address. */
+	long ra,
+	/** Stack pointer. */
+	        sp,
+	/** Global pointer. */
+	        gp,
+	/** Thread pointer. */
+	        tp,
+	/** Temporary 0. */
+	        t0,
+	/** Temporary 1. */
+	        t1,
+	/** Temporary 2. */
+	        t2,
+	/** Caller-save 0. */
+	        s0,
+	/** Caller-save 1. */
+	        s1,
+	/** Argument 0. */
+	        a0,
+	/** Argument 1. */
+	        a1,
+	/** Argument 2. */
+	        a2,
+	/** Argument 3. */
+	        a3,
+	/** Argument 4. */
+	        a4,
+	/** Argument 5. */
+	        a5,
+	/** Argument 6. */
+	        a6,
+	/** Argument 7. */
+	        a7,
+	/** Caller-save 2. */
+	        s2,
+	/** Caller-save 3. */
+	        s3,
+	/** Caller-save 4. */
+	        s4,
+	/** Caller-save 5. */
+	        s5,
+	/** Caller-save 6. */
+	        s6,
+	/** caller-save 7. */
+	        s7,
+	/** Caller-save 8. */
+	        s8,
+	/** Caller-save 9. */
+	        s9,
+	/** Caller-save 10. */
+	        s10,
+	/** Caller-save 11. */
+	        s11,
+	/** Temporary 3. */
+	        t3,
+	/** Temporary 4. */
+	        t4,
+	/** Temporary 5. */
+	        t5,
+	/** Temporary 6. */
+	        t6;
 };
 
 #endif /* APOS_RISCV_REGS_H */