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| author | Kimplul <kimi.h.kuparinen@gmail.com> | 2022-04-24 14:30:04 +0300 |
|---|---|---|
| committer | Kimplul <kimi.h.kuparinen@gmail.com> | 2022-04-24 14:30:04 +0300 |
| commit | 105f3d0dab75f669d1fc404c06b73289b343591c (patch) | |
| tree | 0cb27e308124bdf25daa03cce4a47d06d079026a /arch/riscv64/kernel/head.S | |
| parent | be3696bd5853819212b1240751efd8d85f282c68 (diff) | |
| download | kmi-105f3d0dab75f669d1fc404c06b73289b343591c.tar.gz kmi-105f3d0dab75f669d1fc404c06b73289b343591c.zip | |
fix rv32 compile errors
Diffstat (limited to 'arch/riscv64/kernel/head.S')
| -rw-r--r-- | arch/riscv64/kernel/head.S | 76 |
1 files changed, 42 insertions, 34 deletions
diff --git a/arch/riscv64/kernel/head.S b/arch/riscv64/kernel/head.S index b8ad295..d2a1927 100644 --- a/arch/riscv64/kernel/head.S +++ b/arch/riscv64/kernel/head.S @@ -1,26 +1,34 @@ #include <csr.h> +#if __riscv_xlen == 64 +#define sr sd +#define lr ld +#else +#define sr sw +#define lr lw +#endif + .section .text .global handle_irq handle_irq: addi sp,sp,-144 - sd ra,136(sp) - sd t0,128(sp) - sd t1,120(sp) - sd t2,112(sp) - sd s0,104(sp) - sd a0,96(sp) - sd a1,88(sp) - sd a2,80(sp) - sd a3,72(sp) - sd a4,64(sp) - sd a5,56(sp) - sd a6,48(sp) - sd a7,40(sp) - sd t3,32(sp) - sd t4,24(sp) - sd t5,16(sp) - sd t6,8(sp) + sr ra,136(sp) + sr t0,128(sp) + sr t1,120(sp) + sr t2,112(sp) + sr s0,104(sp) + sr a0,96(sp) + sr a1,88(sp) + sr a2,80(sp) + sr a3,72(sp) + sr a4,64(sp) + sr a5,56(sp) + sr a6,48(sp) + sr a7,40(sp) + sr t3,32(sp) + sr t4,24(sp) + sr t5,16(sp) + sr t6,8(sp) addi s0,sp,144 /* load supervisor cause */ csrr s4, CSR_SCAUSE @@ -40,25 +48,25 @@ handle_syscall: j restore_noreturn restore_all: - ld a0,96(sp) + lr a0,96(sp) restore_noreturn: - ld ra,136(sp) - ld t0,128(sp) - ld t1,120(sp) - ld t2,112(sp) - ld s0,104(sp) - ld a1,88(sp) - ld a2,80(sp) - ld a3,72(sp) - ld a4,64(sp) - ld a5,56(sp) - ld a6,48(sp) - ld a7,40(sp) - ld t3,32(sp) - ld t4,24(sp) - ld t5,16(sp) - ld t6,8(sp) + lr ra,136(sp) + lr t0,128(sp) + lr t1,120(sp) + lr t2,112(sp) + lr s0,104(sp) + lr a1,88(sp) + lr a2,80(sp) + lr a3,72(sp) + lr a4,64(sp) + lr a5,56(sp) + lr a6,48(sp) + lr a7,40(sp) + lr t3,32(sp) + lr t4,24(sp) + lr t5,16(sp) + lr t6,8(sp) addi sp,sp,144 /* assume supervisor for now */ sret |