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| author | Kimplul <kimi.h.kuparinen@gmail.com> | 2022-05-22 23:35:02 +0300 |
|---|---|---|
| committer | Kimplul <kimi.h.kuparinen@gmail.com> | 2022-05-22 23:35:02 +0300 |
| commit | 72df0de8cb579fd96449d19eb57fc71335907a19 (patch) | |
| tree | 6a0a24478fe95f009619787afd24ddfe5df8cfd7 /arch/riscv64/include/regs.h | |
| parent | d99be9e2912e0726ab779053b43a89e3b9e21490 (diff) | |
| download | kmi-72df0de8cb579fd96449d19eb57fc71335907a19.tar.gz kmi-72df0de8cb579fd96449d19eb57fc71335907a19.zip | |
add @file info to all files
+ Next step, start documenting contents of each file.
Diffstat (limited to 'arch/riscv64/include/regs.h')
| -rw-r--r-- | arch/riscv64/include/regs.h | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/arch/riscv64/include/regs.h b/arch/riscv64/include/regs.h index 699af8b..c785ea6 100644 --- a/arch/riscv64/include/regs.h +++ b/arch/riscv64/include/regs.h @@ -1,6 +1,15 @@ #ifndef APOS_RISCV_REGS_H #define APOS_RISCV_REGS_H +/** + * @file regs.h + * riscv64 registers, currently only base extension integer regs. Used to \ref + * _save_context. Used in \ref arch/riscv64/gen/asm-offsets.c to generate a list + * of offsets usable from assembly. + * + * @todo Implement sacing floating point, vector, etc. registers. + */ + struct riscv_regs { long ra, sp, gp, tp, t0, t1, t2, s0, s1, a0, a1, a2, a3, a4, a5, a6, a7, s2, s3, s4, s5, s6, s7, s8, s9, s10, s11, t3, t4, t5, t6; |
