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+ Actual cache still missing, lol
+ Initial performance numbers aren't too promising compared to
simt_riscv64 or even simple_mesh1d, but there's a somewhat
increased latency due to registering inputs and the shared req
logic which can likely be improved. Will have to dig into this a
bit further
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+ Might try to fix it at some point in the future but for now I don't
want to carry around broken code
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+ Seems to decrease performance a little bit, presumably due to
extra register copy, but simplifies code a lot and opens up more
genericism so I'll consider it an upgrade for now. Copying packets
around is rather slow though, might in the future move to some
kind of pointer based packet handling
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+ Kind of like CHERI, but uses out-of-line pointer information.
The idea is that a core that is compatible with ALLOC_IF queries
the allocation tracker if an address is legal and gets a response.
This ideal tracker effectively has infinite memory and doesn't talk to
any other components, but a real implementation might want to limit
the allocations per process or chat with some reserved memory region
somewhere else in the system to maintain a binary tree or something.
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+ Purely virtual, doesn't exist, but would be 'theoretically' ideal.
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+ Previous name was grid
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+ Not quite deadlock free for 2D/3D for whatever reason
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+ As they are currently implemented, grid *may* get stuck if two nodes
try to send to eachother at the same time, I should probably add in
some kind of input buffer as well
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+ Also allow reusing packets, though only with external buffers.
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