add initial simt rv64 core

7 files changed, 507 insertions, 3 deletions

diff --git a/include/gran/cpu/riscv/simt_riscv64.h b/include/gran/cpu/riscv/simt_riscv64.h
new file mode 100644
index 0000000..cd4f195
--- /dev/null
+++ b/include/gran/cpu/riscv/simt_riscv64.h
@@ -0,0 +1,24 @@
+#ifndef GRAN_SIMT_RISCV64_H
+#define GRAN_SIMT_RISCV64_H
+
+#include <stdint.h>
+#include <gran/component.h>
+
+struct simt_riscv64_conf {
+        uint64_t data_rcv;
+        uint64_t inst_rcv;
+        uint64_t start_pc;
+        uint64_t num_lanes;
+};
+
+struct component *create_simt_riscv64(
+                struct simt_riscv64_conf conf,
+                struct component *imem,
+                struct component *dmem);
+
+struct component *simt_riscv64_data_intf(struct component *c);
+struct component *simt_riscv64_inst_intf(struct component *c);
+
+void simt_riscv64_set_reg(struct component *c, size_t lane, size_t reg, uint64_t val);
+
+#endif /* GRAN_SIMT_RISCV64_H */
diff --git a/src/cpu/riscv/simple_riscv64.c b/src/cpu/riscv/simple_riscv64.c
index b2bdff6..fff9a62 100644
--- a/src/cpu/riscv/simple_riscv64.c
+++ b/src/cpu/riscv/simple_riscv64.c
@@ -661,6 +661,9 @@ static stat simple_riscv64_clock(struct simple_riscv64 *cpu)
 		return ENOSUCH;
 	}
 
+	if (ret != OK)
+		return ret;
+
 	if (cpu->ils.state == LDST_IDLE) {
 		cpu->ils.pkt = create_packet(cpu->rcv + 64,
 		                             cpu->pc,
@@ -675,13 +678,16 @@ send:
 		stat ret = SEND(cpu, cpu->imem, cpu->ils.pkt);
 		if (ret == EBUSY) {
 			cpu->ils.state = LDST_BLOCKED;
-			return ret;
+			return OK;
 		}
 
+		if (ret != OK)
+			return ret;
+
 		cpu->ils.state = LDST_SENT;
 	}
 
-	return ret;
+	return OK;
 }
 
 struct component *create_simple_riscv64(uint64_t rcv, uint64_t start_pc,
diff --git a/src/cpu/riscv/simt_riscv64.c b/src/cpu/riscv/simt_riscv64.c
new file mode 100644
index 0000000..68e87a5
--- /dev/null
+++ b/src/cpu/riscv/simt_riscv64.c
@@ -0,0 +1,295 @@
+#include <gran/cpu/riscv/simt_riscv64.h>
+
+/* use simple rv64 cores are lanes for now at least, possibly extend simple
+ * model with some cross-lane interface for barriers etc. */
+#include <gran/cpu/riscv/simple_riscv64.h>
+
+/* vector of riscv cores */
+#define VEC_NAME lanes
+#define VEC_TYPE struct component *
+#include <conts/vec.h>
+
+/* vector of requests */
+struct req {
+	struct reg reg;
+	bool queued;
+};
+
+#define VEC_NAME reqs
+#define VEC_TYPE struct req
+#include <conts/vec.h>
+
+struct simt_riscv64 {
+	struct component component;
+	struct simt_riscv64_conf conf;
+	struct component *imem;
+	struct component *dmem;
+
+	struct lanes lanes;
+
+	struct component imem_intf;
+	struct component dmem_intf;
+
+	struct reqs data_rqs;
+	struct reqs inst_rqs;
+
+	size_t rr;
+};
+
+static stat simt_riscv64_ext_send(uint64_t rcv, struct component *intf, struct component *mem, struct packet pkt)
+{
+	/* do fixups for sending */
+	if (is_set(&pkt, PACKET_READ))
+		pkt.mask = ~0ULL;
+
+	/* smuggle index as receive address */
+	uint32_t i = (uint32_t)(pkt.from >> 32);
+	pkt.from = rcv | i;
+	return SEND(intf, mem, pkt);
+}
+
+static stat simt_riscv64_handle_response(struct simt_riscv64 *c,
+		struct component *intf, struct reqs *reqs,
+		struct packet pkt)
+{
+	/* use index smuggled as address to check which request this is a
+	 * response to */
+	uint32_t idx = (uint32_t)pkt.to;
+	struct req *s = reqs_at(reqs, (size_t)idx);
+
+	/* sanity check response, a bit crude for now */
+	assert(s);
+	assert(s->reg.pkt.to == pkt.from);
+	assert(s->reg.busy == true);
+	assert( is_set(&pkt, PACKET_DONE));
+	assert(!is_set(&pkt, PACKET_ERROR));
+
+	/* reads are always full width to maximize chance of all lanes hitting
+	 * same cacheline.
+	 *
+	 * Probably not ideal for instructions when not lockstepping...?
+	 */
+	assert(is_set(&pkt, PACKET_READ) ? pkt.mask == ~0ULL : 1);
+
+	/* use mask to indicate which portion of packet was meant for
+	 * this lane */
+	pkt.mask = s->reg.pkt.mask;
+
+	/* use original from address */
+	pkt.to = s->reg.pkt.from;
+
+	struct component *lane = *lanes_at(&c->lanes, idx);
+	stat ok = SEND(intf, lane, pkt);
+	assert(ok == OK);
+
+	s->reg.busy = false;
+
+	/* possibly broadcast response to readers */
+	if (is_set(&pkt, PACKET_READ))
+	for (size_t i = 0; i < c->conf.num_lanes; ++i) {
+		struct req *req = reqs_at(reqs, i);
+		if (!req->reg.busy)
+			continue;
+
+		/* 64-byte aligned */
+		if (req->reg.pkt.to != pkt.from)
+			continue;
+
+		/* skip non-reads */
+		if (!is_set(&req->reg.pkt, PACKET_READ))
+			continue;
+
+		struct component *lane = *lanes_at(&c->lanes, i);
+
+		pkt.mask = req->reg.pkt.mask;
+		pkt.to = req->reg.pkt.from;
+
+		stat ok = SEND(intf, lane, pkt);
+		/* no reason for core to be blocked */
+		assert(ok == OK);
+
+		req->reg.busy = false;
+	}
+
+	return OK;
+}
+
+static stat simt_riscv64_receive(struct simt_riscv64 *c,
+		size_t rcv, struct component *mem,
+		struct component *intf, struct reqs *reqs,
+		struct component *from, struct packet pkt)
+{
+	if (mem == from)
+		return simt_riscv64_handle_response(c, intf, reqs, pkt);
+
+	/* handle send */
+	int32_t idx = pkt.from >> 32;
+	struct req *req = reqs_at(reqs, idx);
+	if (req->reg.busy)
+		return EBUSY;
+
+	/* store packet */
+	req->reg.pkt = pkt;
+	req->reg.busy = true;
+	req->queued = false;
+
+	/* check if packet can piggyback off of another packet */
+	if (is_set(&pkt, PACKET_READ))
+	foreach(reqs, other_req, reqs) {
+		/* skip ourselves */
+		if (req == other_req)
+			continue;
+
+		if (!other_req->reg.busy)
+			continue;
+
+		struct packet *other_pkt = &other_req->reg.pkt;
+		if (!is_set(other_pkt, PACKET_READ))
+			continue;
+
+		/* yes, we can piggyback, therefore no need to do anything else */
+		if (pkt.to == other_pkt->to)
+			return OK;
+	}
+
+	stat r = simt_riscv64_ext_send(rcv, intf, mem, pkt);
+	if (r == EBUSY)
+		req->queued = true;
+
+	return r;
+}
+
+static stat simt_riscv64_data_receive(struct component *dmem_intf, struct component *from,
+			 struct packet pkt)
+{
+	struct simt_riscv64 *c = CONTAINER_OF(dmem_intf, struct simt_riscv64, dmem_intf);
+	return simt_riscv64_receive(c, c->conf.data_rcv,
+			c->dmem, &c->dmem_intf, &c->data_rqs,
+			from, pkt
+	);
+}
+
+static stat simt_riscv64_inst_receive(struct component *imem_intf, struct component *from,
+		struct packet pkt)
+{
+	struct simt_riscv64 *c = CONTAINER_OF(imem_intf, struct simt_riscv64, imem_intf);
+	return simt_riscv64_receive(c, c->conf.inst_rcv,
+			c->imem, &c->imem_intf, &c->inst_rqs,
+			from, pkt
+	);
+}
+
+static stat simt_riscv64_clock(struct simt_riscv64 *c)
+{
+	stat r = OK;
+	/* send out queued stuff */
+	foreach(reqs, req, &c->data_rqs) {
+		if (!req->queued)
+			continue;
+
+		r = simt_riscv64_ext_send(c->conf.data_rcv, &c->dmem_intf, c->dmem, req->reg.pkt);
+		if (r == OK) {
+			req->queued = false;
+			continue;
+		}
+
+		if (r == EBUSY)
+			continue;
+
+		return r;
+	}
+
+	foreach(reqs, req, &c->inst_rqs) {
+		if (!req->queued)
+			continue;
+
+		r = simt_riscv64_ext_send(c->conf.inst_rcv, &c->imem_intf, c->imem, req->reg.pkt);
+		if (r == OK) {
+			req->queued = false;
+			continue;
+		}
+
+		if (r == EBUSY)
+			continue;
+
+		return r;
+	}
+
+
+	foreach(lanes, core, &c->lanes) {
+		assert(core);
+
+		if ((r = (*core)->clock(*core)) != OK)
+			return r;
+	}
+
+	return r;
+}
+
+struct component *create_simt_riscv64(
+		struct simt_riscv64_conf conf,
+		struct component *imem,
+		struct component *dmem)
+{
+	struct simt_riscv64 *new = calloc(1, sizeof(struct simt_riscv64));
+	if (!new)
+		return NULL;
+
+	new->component.clock = (clock_callback)simt_riscv64_clock;
+
+	new->conf = conf;
+	new->imem = imem;
+	new->dmem = dmem;
+
+	new->lanes = lanes_create(conf.num_lanes);
+	new->data_rqs = reqs_create(conf.num_lanes);
+	new->inst_rqs = reqs_create(conf.num_lanes);
+
+	new->imem_intf.receive = (receive_callback)simt_riscv64_inst_receive;
+	new->dmem_intf.receive = (receive_callback)simt_riscv64_data_receive;
+
+	new->rr = 0;
+
+	for (uint64_t i = 0; i < conf.num_lanes; ++i) {
+		struct component *core = create_simple_riscv64(
+				/* core ID, should group id also be given? */
+				i << 32,
+				conf.start_pc,
+				&new->imem_intf,
+				&new->dmem_intf
+
+		);
+
+		lanes_append(&new->lanes, core);
+
+		struct req empty = {
+			.reg = {
+				.pkt = {},
+				.busy = false,
+			},
+			.queued = false
+		};
+		reqs_append(&new->data_rqs, empty);
+		reqs_append(&new->inst_rqs, empty);
+	}
+
+	return (struct component *)&new->component;
+}
+
+struct component *simt_riscv64_data_intf(struct component *c)
+{
+	struct simt_riscv64 *rv64 = (struct simt_riscv64 *)c;
+	return &rv64->dmem_intf;
+}
+
+struct component *simt_riscv64_inst_intf(struct component *c)
+{
+	struct simt_riscv64 *rv64 = (struct simt_riscv64 *)c;
+	return &rv64->imem_intf;
+}
+
+void simt_riscv64_set_reg(struct component *c, size_t lane, size_t reg, uint64_t val)
+{
+	struct simt_riscv64 *rv64 = (struct simt_riscv64 *)c;
+	simple_riscv64_set_reg(*lanes_at(&rv64->lanes, lane), reg, val);
+}
diff --git a/src/cpu/riscv/source.mk b/src/cpu/riscv/source.mk
index 57e0bf9..dd3240e 100644
--- a/src/cpu/riscv/source.mk
+++ b/src/cpu/riscv/source.mk
@@ -1 +1,2 @@
-GRAN_SOURCES += src/cpu/riscv/simple_riscv64.c
+GRAN_SOURCES += src/cpu/riscv/simple_riscv64.c \
+		src/cpu/riscv/simt_riscv64.c
diff --git a/tests/simt_riscv64/sim.c b/tests/simt_riscv64/sim.c
new file mode 100644
index 0000000..b161491
--- /dev/null
+++ b/tests/simt_riscv64/sim.c
@@ -0,0 +1,100 @@
+#include <assert.h>
+
+#include <gran/root.h>
+#include <gran/mem/simple_mem.h>
+#include <gran/bus/simple_bus.h>
+#include <gran/uart/simple_uart.h>
+#include <gran/mesh/node1d.h>
+#include <gran/cpu/riscv/simt_riscv64.h>
+
+#include "../build/tests/simt_riscv64/test.inc"
+
+static stat build_simt(struct clock_domain *clk, uint16_t clusters, uint16_t lanes)
+{
+	struct component **mesh = calloc(clusters + 1, sizeof(struct component *));
+	assert(mesh);
+
+	for (int i = 1; i < clusters + 1; ++i) {
+		struct component *node = create_mesh_node1d(i, 3);
+		clock_domain_add(clk, node);
+		mesh[i] = node;
+
+		struct component *mem = create_simple_mem(4096);
+		init_simple_mem(mem, 0,
+				build_tests_simt_riscv64_test_inc_bin_len,
+				build_tests_simt_riscv64_test_inc_bin);
+
+		uint64_t data_rcv = mesh1d_addr(i, 0, 0);
+		uint64_t inst_rcv = mesh1d_addr(i, 1, 0);
+		struct simt_riscv64_conf conf = {
+			.data_rcv  = data_rcv,
+			.inst_rcv  = inst_rcv,
+			.num_lanes = lanes,
+			/* each cluster should request instructions from its own
+			 * instruction memory bank */
+			.start_pc  = mesh1d_addr(i, 2, 0)
+		};
+
+		struct component *rv64 = create_simt_riscv64(conf, node, node);
+		for (int j = 0; j < lanes; ++j) {
+			simt_riscv64_set_reg(rv64, j, 10, i); /* a0 */
+			simt_riscv64_set_reg(rv64, j, 11, j); /* a1 */
+			simt_riscv64_set_reg(rv64, j, 12, clusters); /* a2 */
+			simt_riscv64_set_reg(rv64, j, 13, lanes); /* a3 */
+		}
+
+		clock_domain_add(clk, rv64);
+		clock_domain_add(clk, mem);
+
+		mesh_node1d_connect(node, simt_riscv64_data_intf(rv64), 0);
+		mesh_node1d_connect(node, simt_riscv64_inst_intf(rv64), 1);
+
+		mesh_node1d_connect(node, mem, 2);
+	}
+
+	/* extra I/O node */
+	struct component *node = create_mesh_node1d(0, 2);
+	clock_domain_add(clk, node);
+	mesh[0] = node;
+
+	struct component *uart = create_simple_uart();
+	clock_domain_add(clk, uart);
+	mesh_node1d_connect(node, uart, 0);
+
+	struct component *mem = create_simple_mem(4096);
+	init_simple_mem(mem, 0,
+			build_tests_simt_riscv64_test_inc_bin_len,
+			build_tests_simt_riscv64_test_inc_bin);
+
+	clock_domain_add(clk, mem);
+	mesh_node1d_connect(node, mem, 1);
+
+	for (int i = 0; i < clusters + 1; ++i) {
+		if (i - 1 >= 0)
+			mesh_node1d_connect_south(mesh[i], mesh[i - 1]);
+
+		if (i + 1 < clusters + 1)
+			mesh_node1d_connect_north(mesh[i], mesh[i + 1]);
+	}
+
+	free(mesh);
+	return OK;
+}
+
+int main()
+{
+	struct clock_domain *clk = create_clock_domain(NS(1));
+
+	/* one cluster with four cores + mem for each core (should
+	 * instructions be fetched from cluster local mem?) */
+	stat r = build_simt(clk, 8, 8);
+	assert(r == OK);
+
+	struct gran_root *root = create_root();
+	root_add_clock(root, clk);
+
+	r = root_run(root);
+	assert(r == OK);
+
+	destroy_root(root);
+}
diff --git a/tests/simt_riscv64/source.mk b/tests/simt_riscv64/source.mk
new file mode 100644
index 0000000..e12420b
--- /dev/null
+++ b/tests/simt_riscv64/source.mk
@@ -0,0 +1,11 @@
+SIMT_RISCV64		:= tests/simt_riscv64
+SIMT_RISCV64_SIM	:= $(SIMT_RISCV64)/sim.c
+
+TESTS += $(SIMT_RISCV64)/sim
+
+.PHONY: $(SIMT_RISCV64)/sim
+$(SIMT_RISCV64)/sim: $(SIMT_RISCV64_SIM) libgran.a
+	mkdir -p build/$(SIMT_RISCV64)
+	./scripts/gen-rv64-fw -d build -o $(SIMT_RISCV64)/test.inc $(SIMT_RISCV64)/test.c
+	$(COMPILE_TEST) $(SIMT_RISCV64_SIM) libgran.a -o build/$@
+	./scripts/gen-report -d build $@
diff --git a/tests/simt_riscv64/test.c b/tests/simt_riscv64/test.c
new file mode 100644
index 0000000..df86774
--- /dev/null
+++ b/tests/simt_riscv64/test.c
@@ -0,0 +1,67 @@
+#include <stdint.h>
+
+__attribute__((always_inline))
+static inline uint64_t mesh1d_addr(uint16_t cluster, uint16_t elem,
+                                   uint32_t off)
+{
+	return ((uint64_t)cluster << 48) | ((uint64_t)elem << 32) | off;
+}
+
+__attribute__((always_inline))
+static inline void print_int8(volatile char *uart, unsigned x)
+{
+	char lo_nibble = (x >> 0) & 0xf;
+	char hi_nibble = (x >> 4) & 0xf;
+
+	*uart = hi_nibble < 10 ? hi_nibble + '0' : (hi_nibble - 10) + 'a';
+	*uart = lo_nibble < 10 ? lo_nibble + '0' : (lo_nibble - 10) + 'a';
+}
+
+__attribute__((always_inline))
+static inline void print_addr(volatile char *uart, unsigned x, unsigned y)
+{
+	*uart = '(';
+	print_int8(uart, x);
+	*uart = ',';
+	*uart = ' ';
+	print_int8(uart, y);
+	*uart = ')';
+	*uart = '\n';
+}
+
+__attribute__((always_inline))
+static inline uint64_t wrap(unsigned x, unsigned X)
+{
+	return x + 1 >= X ? 0 : x + 1;
+}
+
+__attribute__((always_inline))
+static inline uint64_t next_idx(unsigned x, unsigned y, unsigned X, unsigned Y)
+{
+	unsigned yi = wrap(y, Y);
+	unsigned xi = yi < y ? wrap(x, X) : x;
+
+	return mesh1d_addr(xi, yi, 0);
+}
+
+void _start(unsigned x, unsigned y, unsigned X, unsigned Y)
+{
+	volatile char *uart = (char *)mesh1d_addr(0, 0, 0);
+	volatile uint64_t *control = (uint64_t *)mesh1d_addr(0, 1, 0);
+
+	if (x == 1 && y == 0) {
+		goto do_work;
+	} else {
+		while (*control != mesh1d_addr(x, y, 0)) {}
+	}
+
+do_work:
+	print_addr(uart, x, y);
+	*control = next_idx(x, y, X, Y);
+
+	if (x == X - 1 && y == Y - 1)
+		asm ("ebreak");
+
+	/* otherwise just loop */
+	while (1) {}
+}