From 82dec45fd786831f791b17b84aedb4d99b5ca25d Mon Sep 17 00:00:00 2001 From: Kimplul Date: Sun, 16 Feb 2025 20:55:24 +0200 Subject: add initial risc-v -> tta translation block --- tb/Makefile | 14 ++++++++++++++ 1 file changed, 14 insertions(+) create mode 100644 tb/Makefile (limited to 'tb/Makefile') diff --git a/tb/Makefile b/tb/Makefile new file mode 100644 index 0000000..a76747f --- /dev/null +++ b/tb/Makefile @@ -0,0 +1,14 @@ +all: rv2insn sched + +.PHONY: sched +sched: sched_tb.sv ../src/sched.sv ../src/common.svh + verilator --Mdir sched_objdir --assert --trace --binary -I../src sched_tb.sv + ./sched_objdir/Vsched_tb + +.PHONY: rv2insn +rv2insn: rv2insn_tb.sv ../src/rv2insn.sv ../src/common.svh + riscv32-unknown-elf-gcc -ffreestanding -nostdlib -march=rv32i -mabi=ilp32 \ + -Wl,-Ttext=0 data/rv2insn.S -o rv2insn + riscv32-unknown-elf-objcopy -O verilog rv2insn rv2insn.hex + verilator --Mdir rv2insn_objdir --assert --trace --binary -I../src rv2insn_tb.sv + ./rv2insn_objdir/Vrv2insn_tb -- cgit v1.2.3