1 files changed, 102 insertions, 0 deletions
diff --git a/src/ttarv32.sv b/src/ttarv32.sv
new file mode 100644
index 0000000..0edf1cb
--- /dev/null
+++ b/src/ttarv32.sv
@@ -0,0 +1,102 @@
+`include "common.svh"
+
+module ttarv32 #(
+	parameter SLOT_COUNT,
+	parameter SLOT_DEPTH,
+	parameter ALU_COUNT
+)(
+	input clk_i,
+	input rst_ni,
+	input rv_t[SLOT_COUNT-1:0] rv_i,
+	output xlen_t pc_o
+);
+
+typedef struct packed {
+	mov_t[1:0] in;
+	mov_t[SLOT_DEPTH-1:0] out;
+	op_t op;
+	imm_t imm;
+} slot_t;
+
+insn_t[SLOT_COUNT-1:0] rv_que;
+
+insn_t[SLOT_COUNT-1:0] prev_que_r;
+insn_t[SLOT_COUNT-1:0] next_que;
+
+slot_t[SLOT_COUNT-1:0] prev_slots_r;
+slot_t[SLOT_COUNT-1:0] next_slots;
+
+xlen_t pc_r;
+
+rv2insn #(
+	.QUE_DEPTH(SLOT_COUNT),
+	.ALU_COUNT(ALU_COUNT)
+) rv2insn (
+	.clk_i(clk_i),
+	.rst_ni(rst_ni),
+	.pc_i(pc_r),
+	.rv_i(rv_i),
+	.que_o(rv_que)
+);
+
+typedef struct packed {
+	insn_t[SLOT_COUNT-1:0] que;
+	xlen_t pc;
+} merge_t;
+
+/* repetition from sched.sv, hmm */
+function automatic insn_t[SLOT_COUNT-1:0] next_insn(insn_t[SLOT_COUNT-1:0] que);
+	return que >> $bits(insn_t);
+endfunction
+
+function automatic logic is_noop(mov_t m);
+	return m.src == NOP && m.dst == NOP;
+endfunction
+
+/* not the best thing in the world but good enough for now */
+function automatic logic is_free(insn_t i);
+	return is_noop(i.in[0]) & is_noop(i.in[1]) & is_noop(i.out);
+endfunction
+
+function automatic merge_t merge(int i,
+	insn_t[SLOT_COUNT-1:0] prev_que, insn_t[SLOT_COUNT-1:0] next_que, xlen_t pc);
+	if (i < SLOT_COUNT) begin
+		logic ok = is_free(prev_que[i]);
+		prev_que[i] = ok ? next_que[0] : prev_que[i];
+		return merge(i + 1,
+			prev_que,
+			ok ? next_insn(next_que) : next_que,
+			ok ? pc + 1 : pc);
+	end else begin
+		return {prev_que, pc};
+	end
+endfunction
+
+merge_t merged;
+assign merged = merge(0, prev_que_r, rv_que, pc_r);
+
+sched #(
+	.QUE_DEPTH(SLOT_COUNT),
+	.SLOT_COUNT(SLOT_COUNT),
+	.SLOT_DEPTH(SLOT_DEPTH),
+	.slot_t(slot_t)
+) sched (
+	.que_i(merged.que),
+	.que_o(next_que),
+	.slots_i(prev_slots_r),
+	.slots_o(next_slots)
+);
+
+always_ff @(posedge clk_i or negedge rst_ni) begin
+	if (!rst_ni) begin
+		prev_slots_r <= 0;
+		prev_que_r <= 0;
+		pc_r <= 0;
+	end else begin
+		prev_slots_r <= next_slots;
+		prev_que_r <= next_que;
+		pc_r <= merged.pc;
+	end
+end
+
+endmodule