`include "common.svh"

module rv2insn_tb;

logic clk;
logic rst_n;

xlen_t pc;
logic[7:0] rv[4*4];
insn_t[3:0] que;

function automatic rv_t[3:0] unp2p(logic[7:0] in[4*4]);
	logic [15:0][7:0] conversion;
	for (int i = 0; i < 4 * 4; ++i) begin
		conversion[i] = in[i];
	end
	return conversion;
endfunction

rv2insn #(
	.QUE_DEPTH(4),
	.ALU_COUNT(2)
) rv2insn (
	.clk_i(clk),
	.rst_ni(rst_n),
	.pc_i(pc),
	.rv_i(unp2p(rv)),
	.que_o(que)
);

initial begin
	$dumpfile("rv2insn_tb.vcd");
	$dumpvars();
	$readmemh("rv2insn.hex", rv);

	clk = 0;
	rst_n = 0;

	#10 rst_n = 1;
	#10 $finish;
end
endmodule