From 0c6297a079795927ea2c85e884aaa57cd5a6ca30 Mon Sep 17 00:00:00 2001 From: Kimplul Date: Tue, 3 Nov 2026 21:32:31 +0200 Subject: compile with verilator -Wall + I also found out that iverilog does not agree with Verilator that the testbenches work (the ones that iverilog can compile, anyway). That's rather annoying, I'm not quite sure what the root cause is. Timing difference in when registers are evaluated versus clock edges or something along those lines? --- tb/Makefile | 24 +++++++++++++++++++----- 1 file changed, 19 insertions(+), 5 deletions(-) (limited to 'tb/Makefile') diff --git a/tb/Makefile b/tb/Makefile index 9f51302..90dbab6 100644 --- a/tb/Makefile +++ b/tb/Makefile @@ -2,7 +2,9 @@ all: rv2insn sched arb ttarv32 router .PHONY: sched sched: sched_tb.sv ../src/sched.sv ../src/common.svh - verilator --Mdir sched_objdir --assert --trace --binary -I../src sched_tb.sv + verilator -Wall --Mdir sched_objdir \ + --assert --trace-fst --trace-structs \ + --binary -I../src sched_tb.sv ./sched_objdir/Vsched_tb .PHONY: rv2insn @@ -10,17 +12,23 @@ rv2insn: rv2insn_tb.sv ../src/rv2insn.sv ../src/common.svh riscv32-unknown-elf-gcc -ffreestanding -nostdlib -march=rv32i -mabi=ilp32 \ -Wl,-Ttext=0 data/rv2insn.S -o rv2insn riscv32-unknown-elf-objcopy -O verilog rv2insn rv2insn.hex - verilator --Mdir rv2insn_objdir --assert --trace --binary -I../src rv2insn_tb.sv + verilator -Wall --Mdir rv2insn_objdir \ + --assert --trace-fst --trace-structs \ + --binary -I../src rv2insn_tb.sv ./rv2insn_objdir/Vrv2insn_tb .PHONY: arb arb: arb_tb.sv ../src/arb.sv - verilator --Mdir arb_objdir --assert --trace --binary -I../src arb_tb.sv + verilator -Wall --Mdir arb_objdir \ + --assert --trace-fst --trace-structs \ + --binary -I../src arb_tb.sv ./arb_objdir/Varb_tb .PHONY: router router: router_tb.sv ../src/router.sv - verilator --Mdir router_objdir --assert --trace --binary -I../src router_tb.sv + verilator -Wall --Mdir router_objdir \ + --assert --trace-fst --trace-structs \ + --binary -I../src router_tb.sv ./router_objdir/Vrouter_tb .PHONY: ttarv32 @@ -28,5 +36,11 @@ ttarv32: ttarv32_tb.sv ../src/ttarv32.sv ../src/rv2insn.sv ../src/sched.sv ../sr riscv32-unknown-elf-gcc -ffreestanding -nostdlib -march=rv32i -mabi=ilp32 \ -Wl,-Ttext=0 data/rv2insn.S -o ttarv32 riscv32-unknown-elf-objcopy -O verilog rv2insn ttarv32.hex - verilator --Mdir ttarv32_objdir --assert --trace --binary -I../src ttarv32_tb.sv + verilator -Wall --Mdir ttarv32_objdir \ + --assert --trace-fst --trace-structs \ + --binary -I../src ttarv32_tb.sv ./ttarv32_objdir/Vttarv32_tb + +.PHONY: clean +clean: + rm -rf *_objdir *.hex *.fst rv2insn ttarv32 -- cgit v1.3