From f4afcfa58eb90d14abd55d79640ecda13b23dc21 Mon Sep 17 00:00:00 2001
From: Kimplul <kimi.h.kuparinen@gmail.com>
Date: Sun, 27 Sep 2026 22:30:41 +0300
Subject: implement circular router

+ Not great latency, but has a fairly high fmax and low resource usage
  on my FPGA, so go with this for now. Likely better suited for data
  path, unsure what I'll do for the control path.
---
 src/common.svh | 2 ++
 1 file changed, 2 insertions(+)

(limited to 'src/common.svh')

diff --git a/src/common.svh b/src/common.svh
index 67a87d2..131a2ca 100644
--- a/src/common.svh
+++ b/src/common.svh
@@ -116,4 +116,6 @@ typedef enum op_t {
 `define rn(r) (REG + port_t'(r))
 `define alu(fu) (ALU + port_t'(fu))
 
+`define COUNTER(x) ((x) > 1 ? $clog2(x) : 1)
+
 `endif /* __COMMON_SVH__ */
-- 
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