From 0c6297a079795927ea2c85e884aaa57cd5a6ca30 Mon Sep 17 00:00:00 2001 From: Kimplul Date: Tue, 3 Nov 2026 21:32:31 +0200 Subject: compile with verilator -Wall + I also found out that iverilog does not agree with Verilator that the testbenches work (the ones that iverilog can compile, anyway). That's rather annoying, I'm not quite sure what the root cause is. Timing difference in when registers are evaluated versus clock edges or something along those lines? --- src/router.sv | 9 +++++---- src/rv2insn.sv | 31 ++++++++++++++++++------------- tb/Makefile | 24 +++++++++++++++++++----- tb/router_tb.sv | 6 ++++-- tb/rv2insn_tb.sv | 8 +++++--- tb/sched_tb.sv | 2 +- tb/ttarv32_tb.sv | 6 +++--- 7 files changed, 55 insertions(+), 31 deletions(-) diff --git a/src/router.sv b/src/router.sv index b496ab9..2783b69 100644 --- a/src/router.sv +++ b/src/router.sv @@ -45,7 +45,6 @@ module router #( ); localparam NW = $bits(addr_i[0].dst.node); -localparam DW = $bits(addr_i[0].dst.dev); typedef struct packed { logic alive; @@ -93,8 +92,8 @@ for (genvar i = 0; i < N + 2; ++i) begin :skidbuffers ); end -for (genvar i = 0; i < N + 2; ++i) -always_comb begin :gen_ring_knot +for (genvar i = 0; i < N + 2; ++i) begin :gen_ring_knot +always_comb begin /* default values */ handle[i] = ring_d[i]; send[i] = 1'b0; @@ -151,10 +150,12 @@ always_comb begin :gen_ring_knot * the ring */ ring_q[(i + 1) % (N + 2)] = recv[i] ? insert[i] : handle[i]; end +end -for (genvar i = 0; i < N + 2; ++i) +for (genvar i = 0; i < N + 2; ++i) begin :gen_ring_ff always_ff @(posedge clk_i or negedge rstx_i) if (!rstx_i) ring_d[i] <= '0; else ring_d[i] <= ring_q[i]; +end endmodule // router diff --git a/src/rv2insn.sv b/src/rv2insn.sv index aeb7a8d..65abfab 100644 --- a/src/rv2insn.sv +++ b/src/rv2insn.sv @@ -28,12 +28,16 @@ function automatic insn_t halt(); return -1; endfunction -function automatic alu_counter_t next_alu(alu_counter_t alu_counter); - return (alu_counter + 1) % ALU_COUNT; +function automatic alu_counter_t next_alu(alu_counter_t c); + return (c + 1) % ALU_COUNT; endfunction -function automatic decode_out_t op_imm(xlen_t pc, itype_t rv, alu_counter_t alu_counter); - alu_counter_t fu = next_alu(alu_counter); +/** verilator warns about unused bits in rv, not sure how to deal with that. + * Explode itype to the relevant bits? Seems verbose, hmm. */ + +/* verilator lint_off UNUSEDSIGNAL */ +function automatic decode_out_t op_imm(xlen_t pc, itype_t rv, alu_counter_t c); + alu_counter_t fu = next_alu(c); unique case (rv.funct3) 3'b000: return {{`rn(rv.rs1), `alu(fu)}, {NOP, NOP}, @@ -45,9 +49,10 @@ function automatic decode_out_t op_imm(xlen_t pc, itype_t rv, alu_counter_t alu_ return 0; endfunction +/* verilator lint_on */ -function automatic decode_out_t op(xlen_t pc, rtype_t rv, alu_counter_t alu_counter); - alu_counter_t fu = next_alu(alu_counter); +function automatic decode_out_t op(xlen_t pc, rtype_t rv, alu_counter_t c); + alu_counter_t fu = next_alu(c); unique case (rv.funct3) 3'b000: begin unique case (rv.funct7) @@ -69,11 +74,11 @@ function automatic decode_out_t op(xlen_t pc, rtype_t rv, alu_counter_t alu_coun endcase endfunction -function automatic decode_out_t decode(xlen_t pc, rv_t rv, alu_counter_t alu_counter); +function automatic decode_out_t decode(xlen_t pc, rv_t rv, alu_counter_t c); unique case (rv[`RV_OP_FIELD]) - OP_IMM: return op_imm (pc, rv, alu_counter); - OP: return op (pc, rv, alu_counter); - default: return {halt(), alu_counter}; + OP_IMM: return op_imm (pc, rv, c); + OP: return op (pc, rv, c); + default: return {halt(), c}; endcase endfunction @@ -83,13 +88,13 @@ typedef struct packed { } stages_out_t; function automatic stages_out_t stages(int i, xlen_t pc, - rv_t[QUE_DEPTH-1:0] rv, insn_t[QUE_DEPTH-1:0] que, alu_counter_t alu_counter); + rv_t[QUE_DEPTH-1:0] rv, insn_t[QUE_DEPTH-1:0] que, alu_counter_t c); if (i < QUE_DEPTH) begin - decode_out_t out = decode(pc + i, rv[i], alu_counter); + decode_out_t out = decode(pc + i, rv[i], c); que[i] = out.insn; return stages(i + 1, pc, rv, que, out.alu_counter); end else begin - return {que, alu_counter}; + return {que, c}; end endfunction diff --git a/tb/Makefile b/tb/Makefile index 9f51302..90dbab6 100644 --- a/tb/Makefile +++ b/tb/Makefile @@ -2,7 +2,9 @@ all: rv2insn sched arb ttarv32 router .PHONY: sched sched: sched_tb.sv ../src/sched.sv ../src/common.svh - verilator --Mdir sched_objdir --assert --trace --binary -I../src sched_tb.sv + verilator -Wall --Mdir sched_objdir \ + --assert --trace-fst --trace-structs \ + --binary -I../src sched_tb.sv ./sched_objdir/Vsched_tb .PHONY: rv2insn @@ -10,17 +12,23 @@ rv2insn: rv2insn_tb.sv ../src/rv2insn.sv ../src/common.svh riscv32-unknown-elf-gcc -ffreestanding -nostdlib -march=rv32i -mabi=ilp32 \ -Wl,-Ttext=0 data/rv2insn.S -o rv2insn riscv32-unknown-elf-objcopy -O verilog rv2insn rv2insn.hex - verilator --Mdir rv2insn_objdir --assert --trace --binary -I../src rv2insn_tb.sv + verilator -Wall --Mdir rv2insn_objdir \ + --assert --trace-fst --trace-structs \ + --binary -I../src rv2insn_tb.sv ./rv2insn_objdir/Vrv2insn_tb .PHONY: arb arb: arb_tb.sv ../src/arb.sv - verilator --Mdir arb_objdir --assert --trace --binary -I../src arb_tb.sv + verilator -Wall --Mdir arb_objdir \ + --assert --trace-fst --trace-structs \ + --binary -I../src arb_tb.sv ./arb_objdir/Varb_tb .PHONY: router router: router_tb.sv ../src/router.sv - verilator --Mdir router_objdir --assert --trace --binary -I../src router_tb.sv + verilator -Wall --Mdir router_objdir \ + --assert --trace-fst --trace-structs \ + --binary -I../src router_tb.sv ./router_objdir/Vrouter_tb .PHONY: ttarv32 @@ -28,5 +36,11 @@ ttarv32: ttarv32_tb.sv ../src/ttarv32.sv ../src/rv2insn.sv ../src/sched.sv ../sr riscv32-unknown-elf-gcc -ffreestanding -nostdlib -march=rv32i -mabi=ilp32 \ -Wl,-Ttext=0 data/rv2insn.S -o ttarv32 riscv32-unknown-elf-objcopy -O verilog rv2insn ttarv32.hex - verilator --Mdir ttarv32_objdir --assert --trace --binary -I../src ttarv32_tb.sv + verilator -Wall --Mdir ttarv32_objdir \ + --assert --trace-fst --trace-structs \ + --binary -I../src ttarv32_tb.sv ./ttarv32_objdir/Vttarv32_tb + +.PHONY: clean +clean: + rm -rf *_objdir *.hex *.fst rv2insn ttarv32 diff --git a/tb/router_tb.sv b/tb/router_tb.sv index ba83568..10bcfdd 100644 --- a/tb/router_tb.sv +++ b/tb/router_tb.sv @@ -79,9 +79,11 @@ assign ready_i[0][0] = ready_o[1][1]; initial begin :test - logic found = 0; + logic found; - $dumpfile("router_tb.vcd"); + found = 0; + + $dumpfile("router_tb.fst"); $dumpvars(); for (int i = 0; i < M; ++i) diff --git a/tb/rv2insn_tb.sv b/tb/rv2insn_tb.sv index 14a0249..243a215 100644 --- a/tb/rv2insn_tb.sv +++ b/tb/rv2insn_tb.sv @@ -7,7 +7,9 @@ logic rst_n; xlen_t pc; logic[7:0] rv[4*4]; -insn_t[3:0] que; +insn_t[3:0] unused_que; + +assign pc = '0; function automatic rv_t[3:0] unp2p(logic[7:0] in[4*4]); logic [15:0][7:0] conversion; @@ -25,11 +27,11 @@ rv2insn #( .rst_ni(rst_n), .pc_i(pc), .rv_i(unp2p(rv)), - .que_o(que) + .que_o(unused_que) ); initial begin - $dumpfile("rv2insn_tb.vcd"); + $dumpfile("rv2insn_tb.fst"); $dumpvars(); $readmemh("rv2insn.hex", rv); diff --git a/tb/sched_tb.sv b/tb/sched_tb.sv index 13c032e..fb79bd3 100644 --- a/tb/sched_tb.sv +++ b/tb/sched_tb.sv @@ -41,7 +41,7 @@ slot_t[1:0] second_check = { }; initial begin - $dumpfile("sched_tb.vcd"); + $dumpfile("sched_tb.fst"); $dumpvars(); clk = 0; diff --git a/tb/ttarv32_tb.sv b/tb/ttarv32_tb.sv index 5b30f25..9ff089d 100644 --- a/tb/ttarv32_tb.sv +++ b/tb/ttarv32_tb.sv @@ -10,7 +10,7 @@ function automatic rv_t[3:0] unp2p(logic[7:0] in[4*4]); return conversion; endfunction -xlen_t pc; +xlen_t unused_pc; logic[7:0] rv[4*4]; logic clk; @@ -23,11 +23,11 @@ ttarv32 #( .clk_i(clk), .rst_ni(rst_n), .rv_i(unp2p(rv)), - .pc_o(pc) + .pc_o(unused_pc) ); initial begin - $dumpfile("ttarv32_tb.vcd"); + $dumpfile("ttarv32_tb.fst"); $dumpvars(); $readmemh("ttarv32.hex", rv); -- cgit v1.3