ttarv32 - GOOFING OFF - Getting familiar with SystemVerilog by writing an in-order multi-issue rv32 core

Age	Commit message (Collapse)	Author
11 days	fix missing connection in skid buffer	Kimplul
	+ Verilator does not check undefined values and unused wire warnings only show up with -Wall (as warnings) so I just missed this completely, hah. Surprised the testbench passed, I guess it's just not quite up to snuff.
2026-09-27	implement circular router	Kimplul
	+ Not great latency, but has a fairly high fmax and low resource usage on my FPGA, so go with this for now. Likely better suited for data path, unsure what I'll do for the control path.