| Age | Commit message (Collapse) | Author | |
|---|---|---|---|
| 14 days | decrease max path lengthHEADmaster | Kimplul | |
| + Not fully functional, but good enough for now | |||
| 2025-02-16 | add some kind of toplevel | Kimplul | |
| 2025-02-16 | add initial risc-v -> tta translation block | Kimplul | |
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index : ttarv32 | |
| Getting familiar with SystemVerilog by writing an in-order multi-issue rv32 core | kimi.h.kuparinen+ttarv32@gmail.com |
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