| Age | Commit message (Collapse) | Author | |
|---|---|---|---|
| 11 days | compile with verilator -WallHEADmaster | Kimplul | |
| + I also found out that iverilog does not agree with Verilator that the testbenches work (the ones that iverilog can compile, anyway). That's rather annoying, I'm not quite sure what the root cause is. Timing difference in when registers are evaluated versus clock edges or something along those lines? | |||
| 2026-07-22 | fix some verilator 5.048 warnings | Kimplul | |
| 2025-08-10 | decrease max path length | Kimplul | |
| + Not fully functional, but good enough for now | |||
| 2025-02-16 | add some kind of toplevel | Kimplul | |
| 2025-02-16 | add initial risc-v -> tta translation block | Kimplul | |
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index : ttarv32 | |
| GOOFING OFF - Getting familiar with SystemVerilog by writing an in-order multi-issue rv32 core | kimi.h.kuparinen+ttarv32@gmail.com |
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