| Age | Commit message (Collapse) | Author | |
|---|---|---|---|
| 11 days | implement circular routerHEADmaster | Kimplul | |
| + Not great latency, but has a fairly high fmax and low resource usage on my FPGA, so go with this for now. Likely better suited for data path, unsure what I'll do for the control path. | |||
| 2026-07-22 | simplift arb | Kimplul | |
| + Had a higher fMax and smaller area compared to previous attempt, at least when synthesized with OpenROAD | |||
| 2026-07-22 | add fst to .gitignore | Kimplul | |
| 2026-07-22 | fix some verilator 5.048 warnings | Kimplul | |
| 2026-06-22 | add simple round-robin arbiter | Kimplul | |
| + Should check how well it synthesises with OpenROAD or something, Vivado seemed to kind of choke on it and it was way slower/bigger than I was expecting. | |||
| 2025-08-10 | decrease max path length | Kimplul | |
| + Not fully functional, but good enough for now | |||
| 2025-02-16 | add some kind of toplevel | Kimplul | |
| 2025-02-16 | add initial risc-v -> tta translation block | Kimplul | |
| 2025-02-15 | initial scheduler | Kimplul | |
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index : ttarv32 | |
| GOOFING OFF - Getting familiar with SystemVerilog by writing an in-order multi-issue rv32 core | kimi.h.kuparinen+ttarv32@gmail.com |
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