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| -rw-r--r-- | .gitignore | 1 |
1 files changed, 1 insertions, 0 deletions
@@ -1,5 +1,6 @@ tb/rv2insn tb/ttarv32 tb/*.vcd +tb/*.fst tb/*.hex tb/*objdir |
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index : ttarv32 | |
| Getting familiar with SystemVerilog by writing an in-order multi-issue rv32 core | kimi.h.kuparinen+ttarv32@gmail.com |
| summaryrefslogtreecommitdiff |
| -rw-r--r-- | .gitignore | 1 |
@@ -1,5 +1,6 @@ tb/rv2insn tb/ttarv32 tb/*.vcd +tb/*.fst tb/*.hex tb/*objdir |