ttarv32/tb/Makefile, branch masterGOOFING OFF - Getting familiar with SystemVerilog by writing an in-order multi-issue rv32 corehttps://metanimi.dy.fi/cgit/ttarv32/atom?h=master2026-11-03T19:32:31Zcompile with verilator -Wall2026-11-03T19:32:31ZKimplulkimi.h.kuparinen@gmail.com2026-11-03T19:32:31Zurn:sha1:0c6297a079795927ea2c85e884aaa57cd5a6ca30
+ I also found out that iverilog does not agree with Verilator that the
testbenches work (the ones that iverilog can compile, anyway). That's
rather annoying, I'm not quite sure what the root cause is. Timing
difference in when registers are evaluated versus clock edges or
something along those lines?
implement circular router2026-09-27T19:30:41ZKimplulkimi.h.kuparinen@gmail.com2026-09-27T19:30:41Zurn:sha1:f4afcfa58eb90d14abd55d79640ecda13b23dc21
+ Not great latency, but has a fairly high fmax and low resource usage
on my FPGA, so go with this for now. Likely better suited for data
path, unsure what I'll do for the control path.
add simple round-robin arbiter2026-06-21T21:53:51ZKimplulkimi.h.kuparinen@gmail.com2026-06-21T21:50:26Zurn:sha1:76029b9bc1242a9292905cae6f71e080955ceaf2
+ Should check how well it synthesises with OpenROAD or something,
Vivado seemed to kind of choke on it and it was way slower/bigger than
I was expecting.
add some kind of toplevel2025-02-16T20:36:57ZKimplulkimi.h.kuparinen@gmail.com2025-02-16T20:36:57Zurn:sha1:373edb42380875eafc8b9de54d80b939d263d041add initial risc-v -> tta translation block2025-02-16T18:55:24ZKimplulkimi.h.kuparinen@gmail.com2025-02-16T18:55:24Zurn:sha1:82dec45fd786831f791b17b84aedb4d99b5ca25d