ttarv32/src, branch masterGOOFING OFF - Getting familiar with SystemVerilog by writing an in-order multi-issue rv32 corehttps://metanimi.dy.fi/cgit/ttarv32/atom?h=master2026-11-03T19:32:31Zcompile with verilator -Wall2026-11-03T19:32:31ZKimplulkimi.h.kuparinen@gmail.com2026-11-03T19:32:31Zurn:sha1:0c6297a079795927ea2c85e884aaa57cd5a6ca30
+ I also found out that iverilog does not agree with Verilator that the
testbenches work (the ones that iverilog can compile, anyway). That's
rather annoying, I'm not quite sure what the root cause is. Timing
difference in when registers are evaluated versus clock edges or
something along those lines?
fix missing connection in skid buffer2026-11-03T18:03:50ZKimplulkimi.h.kuparinen@gmail.com2026-11-03T18:03:50Zurn:sha1:b9afe2d4c22e35f2d2e65d67c07b300ba3f7ccb3
+ Verilator does not check undefined values and unused wire warnings
only show up with -Wall (as warnings) so I just missed this
completely, hah. Surprised the testbench passed, I guess it's just not
quite up to snuff.
implement circular router2026-09-27T19:30:41ZKimplulkimi.h.kuparinen@gmail.com2026-09-27T19:30:41Zurn:sha1:f4afcfa58eb90d14abd55d79640ecda13b23dc21
+ Not great latency, but has a fairly high fmax and low resource usage
on my FPGA, so go with this for now. Likely better suited for data
path, unsure what I'll do for the control path.
simplift arb2026-07-22T17:56:59ZKimplulkimi.h.kuparinen@gmail.com2026-07-22T17:56:59Zurn:sha1:bc5941a1fcfd0a607a6aef51f7659c3f233b65dc
+ Had a higher fMax and smaller area compared to previous attempt,
at least when synthesized with OpenROAD
fix some verilator 5.048 warnings2026-07-22T17:56:11ZKimplulkimi.h.kuparinen@gmail.com2026-07-22T17:56:11Zurn:sha1:b7678edeb8ac8d7b95719988c9bdaf52b734c212add simple round-robin arbiter2026-06-21T21:53:51ZKimplulkimi.h.kuparinen@gmail.com2026-06-21T21:50:26Zurn:sha1:76029b9bc1242a9292905cae6f71e080955ceaf2
+ Should check how well it synthesises with OpenROAD or something,
Vivado seemed to kind of choke on it and it was way slower/bigger than
I was expecting.
decrease max path length2025-08-10T17:16:09ZKimplulkimi.h.kuparinen@gmail.com2025-08-10T17:16:09Zurn:sha1:b1ee83cd1ea325a5d353365ac35790a7c1d47845
+ Not fully functional, but good enough for now
add some kind of toplevel2025-02-16T20:36:57ZKimplulkimi.h.kuparinen@gmail.com2025-02-16T20:36:57Zurn:sha1:373edb42380875eafc8b9de54d80b939d263d041add initial risc-v -> tta translation block2025-02-16T18:55:24ZKimplulkimi.h.kuparinen@gmail.com2025-02-16T18:55:24Zurn:sha1:82dec45fd786831f791b17b84aedb4d99b5ca25dinitial scheduler2025-02-15T19:54:16ZKimplulkimi.h.kuparinen@gmail.com2025-02-15T19:54:16Zurn:sha1:0141d830f3326594f159c627dbbc284fdef27674