ttarv32/src/skid_buffer.sv, branch masterGOOFING OFF - Getting familiar with SystemVerilog by writing an in-order multi-issue rv32 corehttps://metanimi.dy.fi/cgit/ttarv32/atom?h=master2026-09-27T19:30:41Zimplement circular router2026-09-27T19:30:41ZKimplulkimi.h.kuparinen@gmail.com2026-09-27T19:30:41Zurn:sha1:f4afcfa58eb90d14abd55d79640ecda13b23dc21
+ Not great latency, but has a fairly high fmax and low resource usage
on my FPGA, so go with this for now. Likely better suited for data
path, unsure what I'll do for the control path.