ttarv32/src/arb.sv, branch master Getting familiar with SystemVerilog by writing an in-order multi-issue rv32 core https://metanimi.dy.fi/cgit/ttarv32/atom?h=master 2026-07-22T17:56:59Z simplift arb 2026-07-22T17:56:59Z Kimplul kimi.h.kuparinen@gmail.com 2026-07-22T17:56:59Z urn:sha1:bc5941a1fcfd0a607a6aef51f7659c3f233b65dc + Had a higher fMax and smaller area compared to previous attempt, at least when synthesized with OpenROAD add simple round-robin arbiter 2026-06-21T21:53:51Z Kimplul kimi.h.kuparinen@gmail.com 2026-06-21T21:50:26Z urn:sha1:76029b9bc1242a9292905cae6f71e080955ceaf2 + Should check how well it synthesises with OpenROAD or something, Vivado seemed to kind of choke on it and it was way slower/bigger than I was expecting.