From c7df9ae5f60ef1d36a20dbfbb8b4b0f4cd1a601a Mon Sep 17 00:00:00 2001 From: Kimplul Date: Sun, 4 Jun 2023 17:43:32 +0300 Subject: add some docs about visionfive2 --- arch/riscv64/conf/init | Bin 3600 -> 3648 bytes arch/riscv64/conf/init.c | 7 ++++++- arch/riscv64/conf/initrd | Bin 4096 -> 4096 bytes 3 files changed, 6 insertions(+), 1 deletion(-) (limited to 'arch/riscv64') diff --git a/arch/riscv64/conf/init b/arch/riscv64/conf/init index c77c048..76de753 100755 Binary files a/arch/riscv64/conf/init and b/arch/riscv64/conf/init differ diff --git a/arch/riscv64/conf/init.c b/arch/riscv64/conf/init.c index b2f4024..8177992 100644 --- a/arch/riscv64/conf/init.c +++ b/arch/riscv64/conf/init.c @@ -256,6 +256,8 @@ void callback(long status, long tid, long d0, long d1, long d2, long d3) #define csr_read(csr, \ res) __asm__ volatile ("csrr %0, " csr : "=r" (res) :: "memory") +#define CSR_CYCLE "0xc00" + void _start() { sys_noop(); @@ -264,17 +266,20 @@ void _start() uint64_t second = sys_timebase(); print_value("Timebase", second); - uint64_t n = 0, i, start; + uint64_t n = 0, i, start, cn, cstart, cend; start = i = sys_ticks(); print_value("Start ticks", start); + csr_read(CSR_CYCLE, cstart); while (i < start + second) { i = sys_ticks(); n++; } + csr_read(CSR_CYCLE, cend); print_value("End ticks", i); print_value("Syscalls per second", n); + print_value("Executed cycles per second", cend - cstart); puts("Setting callback..."); sys_ipc_server(callback); diff --git a/arch/riscv64/conf/initrd b/arch/riscv64/conf/initrd index fb6f525..e4d76a2 100644 Binary files a/arch/riscv64/conf/initrd and b/arch/riscv64/conf/initrd differ -- cgit v1.3