From 960330c5d843d1aa96aa191fc27f72da563293ea Mon Sep 17 00:00:00 2001 From: Kimplul Date: Mon, 23 May 2022 21:31:48 +0300 Subject: new include structure, make parse easier for doxy --- arch/riscv64/include/arch.h | 8 +++++ arch/riscv64/include/csr.h | 69 --------------------------------------- arch/riscv64/include/gen/.gitkeep | 0 arch/riscv64/include/irq.h | 8 +++++ arch/riscv64/include/pages.h | 49 --------------------------- arch/riscv64/include/regs.h | 18 ---------- arch/riscv64/include/sbi.h | 57 -------------------------------- arch/riscv64/include/timer.h | 8 +++++ 8 files changed, 24 insertions(+), 193 deletions(-) create mode 100644 arch/riscv64/include/arch.h delete mode 100644 arch/riscv64/include/csr.h delete mode 100644 arch/riscv64/include/gen/.gitkeep create mode 100644 arch/riscv64/include/irq.h delete mode 100644 arch/riscv64/include/pages.h delete mode 100644 arch/riscv64/include/regs.h delete mode 100644 arch/riscv64/include/sbi.h create mode 100644 arch/riscv64/include/timer.h (limited to 'arch/riscv64/include') diff --git a/arch/riscv64/include/arch.h b/arch/riscv64/include/arch.h new file mode 100644 index 0000000..0930543 --- /dev/null +++ b/arch/riscv64/include/arch.h @@ -0,0 +1,8 @@ +#ifndef APOS_RISCV_ARCH_H +#define APOS_RISCV_ARCH_H +/** + * @file arch.h + * riscv64 arch header, currently empty but kept around for forwards + * compatibility. + */ +#endif /* APOS_RISCV_ARCH_H */ diff --git a/arch/riscv64/include/csr.h b/arch/riscv64/include/csr.h deleted file mode 100644 index ade397c..0000000 --- a/arch/riscv64/include/csr.h +++ /dev/null @@ -1,69 +0,0 @@ -#ifndef APOS_CSR_H -#define APOS_CSR_H - -/** - * @file csr.h - * riscv64-specific header for CSR handling - */ - -#define SATP_MODE_Sv32 0x80000000 -#define SATP_MODE_Sv39 0x8000000000000000 -#define SATP_MODE_Sv48 0x9000000000000000 - -/* unprivileged CSR registers */ -#define CSR_TIME 0xc01 -#define CSR_TIMEH 0xc81 - -/* supervisor CSR registers */ -#define CSR_SSTATUS 0x100 -#define CSR_SIE 0x104 -#define CSR_STVEC 0x105 -#define CSR_SCOUNTEREN 0x106 - -#define CSR_SENVCFG 0x10A - -#define CSR_SSCRATCH 0x140 -#define CSR_SEPC 0x141 -#define CSR_SCAUSE 0x142 -#define CSR_STVAL 0x143 -#define CSR_SIP 0x144 - -#define CSR_SATP 0x180 - -#define CSR_SCONTEXT 0x5A8 - -/* Exception causes */ -#define EXC_INST_MISALIGNED 0 -#define EXC_INST_ACCESS 1 -#define EXC_BREAKPOINT 3 -#define EXC_LOAD_ACCESS 5 -#define EXC_STORE_ACCESS 7 -#define EXC_SYSCALL 8 -#define EXC_INST_PAGE_FAULT 12 -#define EXC_LOAD_PAGE_FAULT 13 -#define EXC_STORE_PAGE_FAULT 15 - -/* status CSR bits */ -#define SSTATUS_SUM (1 << 18) -#define SSTATUS_SPP (1 << 8) - -/* directly lifted from Linux:/arch/riscv/include/asm/asm.h:9-13 */ -#if defined(__ASSEMBLY__) -#define __ASM_STR(x) x -#else -#define __ASM_STR(x) #x -#endif - -#define csr_read(csr, res) \ - __asm__ volatile ("csrr %0, " __ASM_STR(csr) : "=r" (res) : : "memory") - -#define csr_write(csr, val) \ - __asm__ volatile ("csrw " __ASM_STR(csr) ", %0" : : "r" (val) : "memory") - -#define csr_set(csr, val) \ - __asm__ volatile ("csrs " __ASM_STR(csr) ", %0" : : "r" (val) : "memory") - -#define csr_clear(csr, val) \ - __asm__ volatile ("csrc " __ASM_STR(csr) ", %0" : : "r" (val) : "memory") - -#endif /* APOS_CSR_H */ diff --git a/arch/riscv64/include/gen/.gitkeep b/arch/riscv64/include/gen/.gitkeep deleted file mode 100644 index e69de29..0000000 diff --git a/arch/riscv64/include/irq.h b/arch/riscv64/include/irq.h new file mode 100644 index 0000000..95ce62a --- /dev/null +++ b/arch/riscv64/include/irq.h @@ -0,0 +1,8 @@ +#ifndef APOS_RISCV_IRQ_H +#define APOS_RISCV_IRQ_H +/** + * @file irq.h + * riscv64 irq header, currently empty but kept around for forwards + * compatibility. + */ +#endif /* APOS_RISCV_IRQ_H */ diff --git a/arch/riscv64/include/pages.h b/arch/riscv64/include/pages.h deleted file mode 100644 index 3f4b632..0000000 --- a/arch/riscv64/include/pages.h +++ /dev/null @@ -1,49 +0,0 @@ -#ifndef APOS_RISCV_PAGES_H -#define APOS_RISCV_PAGES_H - -/** - * @file pages.h - * riscv64-specific shorthands for some page sizes. - */ - -/** - * riscv64 4KiB page, order 0. - */ -#define MM_KPAGE MM_O0 - -/** - * riscv64 2MiB page, order 1. - */ -#define MM_MPAGE MM_O1 - -/** - * riscv64 1GiB page, order 2. - */ -#define MM_GPAGE MM_O2 - -/** - * riscv64 512GiB page, order 3. - */ -#define MM_TPAGE MM_O3 - -/** - * riscv64 4KiB page size. - */ -#define MM_KPAGE_SIZE SZ_4K - -/** - * riscv64 2MiB page size. - */ -#define MM_MPAGE_SIZE SZ_2M - -/** - * riscv64 1GiB page size. - */ -#define MM_GPAGE_SIZE SZ_1G - -/** - * riscv64 512GiB page size. - */ -#define MM_TPAGE_SIZE SZ_512G - -#endif /* APOS_RISCV_PAGES_H */ diff --git a/arch/riscv64/include/regs.h b/arch/riscv64/include/regs.h deleted file mode 100644 index 511934e..0000000 --- a/arch/riscv64/include/regs.h +++ /dev/null @@ -1,18 +0,0 @@ -#ifndef APOS_RISCV_REGS_H -#define APOS_RISCV_REGS_H - -/** - * @file regs.h - * riscv64 registers, currently only base extension integer regs. Used to \ref - * _save_context. Used in \ref arch/riscv64/gen/asm-offsets.c to generate a list - * of offsets usable from assembly. - * - * @todo Implement sacing floating point, vector, etc. registers. - */ - -struct riscv_regs { - long ra, sp, gp, tp, t0, t1, t2, s0, s1, a0, a1, a2, a3, a4, a5, a6, a7, - s2, s3, s4, s5, s6, s7, s8, s9, s10, s11, t3, t4, t5, t6; -}; - -#endif /* APOS_RISCV_REGS_H */ diff --git a/arch/riscv64/include/sbi.h b/arch/riscv64/include/sbi.h deleted file mode 100644 index 44eec4f..0000000 --- a/arch/riscv64/include/sbi.h +++ /dev/null @@ -1,57 +0,0 @@ -#ifndef APOS_RISCV_SBI_H -#define APOS_RISCV_SBI_H - -/** - * @file sbi.h - * riscv64-specific OpenSBI definitions. - */ - -#include - -struct sbiret { - long error; - long value; -}; - -enum { - SBI_SUCCESS = 0, - SBI_ERR_FAILED = -1, - SBI_ERR_NOT_SUPPORTED = -2, - SBI_ERR_INVALID_PARAM = -3, - SBI_ERR_DENIED = -4, - SBI_ERR_INVALID_ADDRESS = -5, - SBI_ERR_ALREADY_AVAILABLE = -6, - SBI_ERR_ALREADY_STARTED = -7, - SBI_ERR_ALREADY_STOPEED = -8, -}; - -/* TODO: query which extensions are available */ -struct sbiret sbi_ecall(int ext, int fid, unsigned long arg0, - unsigned long arg1, unsigned long arg2, - unsigned long arg3, unsigned long arg4, - unsigned long arg5); - -#define EID_TIME 0x54494D45 -#define FID_SET_TIMER 0 -static inline struct sbiret sbi_set_timer(uint64_t stime_value) -{ - /* TODO: read timebase from fdt, seems to be clocks/sec for accurate - * timers */ -#if __riscv_xlen == 32 - return sbi_ecall(EID_TIME, FID_SET_TIMER, stime_value, - stime_value >> 32, 0, 0, 0, 0); -#else - return sbi_ecall(EID_TIME, FID_SET_TIMER, stime_value, 0, 0, 0, 0, 0); -#endif -} - -#define EID_SRST 0x53525354 -#define FID_RESET 0 -static inline struct sbiret sbi_system_reset(uint32_t reset_type, - uint32_t reset_reason) -{ - return sbi_ecall(EID_SRST, FID_RESET, reset_type, reset_reason, 0, 0, 0, - 0); -} - -#endif /* APOS_RISCV_SBI_H */ diff --git a/arch/riscv64/include/timer.h b/arch/riscv64/include/timer.h new file mode 100644 index 0000000..2e468ba --- /dev/null +++ b/arch/riscv64/include/timer.h @@ -0,0 +1,8 @@ +#ifndef APOS_RISCV_TIMER_H +#define APOS_RISCV_TIMER_H +/** + * @file timer.h + * riscv64 timer header, currently empty but kept around for forwards + * compatibility. + */ +#endif /* APOS_RISCV_TIMER_H */ -- cgit v1.3