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2024-06-01document sleepKimplul
2024-06-01add sleep syscallKimplul
+ Sets the current core to sleep
2024-05-10update formatting configKimplul
2024-01-10some kmx alleviationsKimplul
2023-10-09experimenting with removing lists threads per procKimplul
+ Gives a very slight improvement to RPC speeds, but mostly cleans up code a little bit.
2023-10-09move rpc stack handling to arch-specific codeKimplul
+ Fairly considerable speedup, as we don't have to look up the rpc pte every time separately, instead cacheing them. Adds an architecture specific limitation to total rpc stack size, though.
2023-08-04fix warnings in smp.cKimplul
+ Only occur with my version of riscv64-linux-gnu-gcc. Funny, that.
2023-08-04add initial smp bringupKimplul
2023-08-03add sbi_hart_startKimplul
2023-08-03fix cpu_send_ipiKimplul
2023-07-31start working on irqsKimplul
2023-07-27use nifty variable argument count trickKimplul
+ Found it in newlib. This allows the compiler to more effectively optimize away unnecessary register operations. Applied to both kernel and init.c for a slight speed increase. I really should move init.c to some other repository though, the binary files are starting to get annoying
2023-06-08skip saving registers when possibleKimplul
2023-06-08add fast userspace return to do_ipcKimplul
2023-06-07change register save/load to increasing orderKimplul
2023-06-04slight optimization and brainfart fixKimplul
2023-06-04visionfive2 bootsKimplul
+ Make 8250 serial driver more generic + Still TODO: write a tutorial on how to boot on the visionfive2
2023-06-04visionfive2 boots until debugging is initializedKimplul
2023-05-29start trying to boot on visionfive 2Kimplul
+ Not bootable quite yet. Among other things, I couldn't get the current starfive u-boot fork to boot, so try adding support for booting with precompiled u-boot via the `go` command. Initial testing with qemu shows that this should be possible, and if it works, might be useful in the (far) future with other slightly janky SBCs. Also, NS16550 is 8250-based, and I'm really only using the base 8250, so rename and add visionfive 2 uart to list of compatibles. Visionfive 2 is still completely untested.
2023-05-17align handle_irq to four byte boundaries alwaysKimplul
+ CSR_STVEC requires four byte alignment
2023-05-12fix LLVM compilationKimplul
+ RELEASE=1 doesn't work for some reason, though
2023-05-11arbitrary load address and RAM base detectionKimplul
+ Both kind of go hand in hand, made sense to do both at the same time. Some parts feel slightly hacky, the loader works by placing everything on the stack and avoiding global values. Still, seems to work?
2023-05-01update license stuffKimplul
2023-04-30rename to kmiKimplul
2022-12-01start looking into memory handlingKimplul
+ Now 10M alloc/frees succeed, which totals more memory than the virtual machine has, so no too obvious leaks are occuring. For future debugging speed, changed 10M to 1M. + Also quick fix to rpcs, stacks are now assigned. Not entirely sure why they worked before this, but good that I found it.
2022-11-21fix llvmKimplul
2022-11-21make syscall handlers voidKimplul
2022-11-21possible optimisationsKimplul
2022-11-13improve documentation on new featuresKimplul
2022-11-13~1.3M ipc requestsKimplul
+ The secret is using gravestones. I'll have to write up full documentation for the feature but essentially riscv lets us encode whatever we want into page table entries, as long as they're not active. We use this to encode highest user address that is not a zero, in that all entries in the top level are either active or gravestones. When an active entry is removed, it is either a gravestone (if there are other active entries above it) or it starts a cascade of removing entries that have been previously removed Slight runtime overhead to page mapping, pretty major advantage in rpc calls. Feature will need to be tested more thorougly, and the init program is sort of a best scenario with just one top level userspace page table entry active at a time, leading to incredibly fast context switches. Current implementation limits a process' max virtual memory to 248 GiB (in Sv39), but I don't think the missing 8 GiB is that big of a deal.
2022-11-13~700k ipc requestsKimplul
+ Eliminated need for save/load_regs, now the register save area is behind a pointer which _slightly_ increases overall syscall delay, but speeds up ipc requests by a fair bit.
2022-11-13give uvmem_map more fitting nameKimplul
+ It really only works with Sv39, I suppose similar structures should be added for Sv4} etc. if I ever get around to it.
2022-11-13write init more sensiblyKimplul
+ Both easier to look at and now the userspace doesn't play as big of a role in the 'benchmarking' with optimizations turned on.
2022-11-12release mode, ~600k requestsKimplul
2022-11-12slight optimizationKimplul
2022-11-12initial rpc implementationsKimplul
2022-11-11less buggy forkKimplul
+ Not strictly done yet, but we can swap between two processes :D
2022-11-09add basic IPI structureKimplul
2022-10-29rewrite pmemKimplul
2022-10-22start outlining ipcKimplul
2022-10-22create impl and CAP_PROC checkingKimplul
2022-10-22initial high level fork impKimplul
2022-10-21beautificationKimplul
2022-10-21initial implementation of swapKimplul
+ Slightly unsure if it should be a syscall, or if assign would be enough. Also, which thread should run in a fork/spawn? For now, old thread, though this might increase latency. Or add swap flag to these calls?
2022-10-21initial spawn implementationKimplul
2022-10-21slight optimisation to cur_tcb on riscvKimplul
2022-09-15change syscalls to take 5 params and return 6Kimplul
+ In total, a syscall is built up of 6 values, with the first being the syscall number. Symmetrically, the first value is now a status and the following five values return "values". This allows us to cram in more info into the ipc_* functions. The performance difference is absolutely minimal, at least from my testing in qemu.
2022-09-14add putch syscall for easier userspace debuggingKimplul
+ Note that it is NOT intended for end user usage, just for debugging.
2022-09-14add canary to kernel stackKimplul
2022-09-14riscv32 boots and advances as far as riscv64Kimplul