kmi/arch/riscv64/source.mk, branch masterACTIVE - Kernel with migrating threads as IPChttps://metanimi.dy.fi/cgit/kmi/atom?h=master2024-08-30T15:52:55Zspecify mabi and march2024-08-30T15:52:55ZKimplulkimi.h.kuparinen@gmail.com2024-08-30T15:52:55Zurn:sha1:5cc76c436fa1234323bad51d72d1291d95991da6cleanup riscv64/conf2024-07-17T16:34:03ZKimplulkimi.h.kuparinen@gmail.com2024-07-17T16:34:03Zurn:sha1:83f8e82c421fa9013ac813b1560abf1c749822cafix LLVM2024-07-08T15:04:03ZKimplulkimi.h.kuparinen@gmail.com2024-07-08T14:43:59Zurn:sha1:e134202611a50b358c147c92bfb8a7f443030b8b
+ Anything extern is right out as LLVM doesn't produce correct code for
them. Maybe if I added some extra attributes but I'm skeptical.
Replaced with static variables and getters/setters.
+ Inline ASM is apparently a bit buggy, so use an assembly stub when jumping to init.
+ Minimize work done in main() to minimize chance of LLVM doing something silly.
Still not 100% certain that I shouldn't just write the main() as an assembly stub
in arch/riscv64 to be absolutely sure everything works as intended.
+ Make .kernel.start section SHF_ALLOC, otherwise lld complains about
pc-relative addressing
Probably some other stuff as well that I'm forgetting right now. But at least with
LLVM14 LTO seems to work, which is pretty cool?
core bringup + various warnings2024-07-06T20:37:11ZKimplulkimi.h.kuparinen@gmail.com2024-07-06T20:37:11Zurn:sha1:3fedbb6e1f849c5e0a4033d68201d60c2fc48121
+ dbg_fdt() is apparently broken, possibly due to UB or something, but
it causes some issues with optimizations enabled. Remove it
temporarily
slight improvements to building2023-06-07T18:30:44ZKimplulkimi.h.kuparinen@gmail.com2023-06-07T18:30:44Zurn:sha1:4b3799eaf4b7ef32eaf40910a7abf2719ce0fa6c
+ User can now specify debug, release and assert handling
disable LTO with LLVM2023-05-11T21:43:03ZKimplulkimi.h.kuparinen@gmail.com2023-05-11T21:43:03Zurn:sha1:50693b398afd65120f6ac62b9b28c7af7765c75afix LLVM compilation2023-05-11T21:36:18ZKimplulkimi.h.kuparinen@gmail.com2023-05-11T21:36:18Zurn:sha1:4cde8bceb1ff14896884c224850f6c7611551175
+ RELEASE=1 doesn't work for some reason, though
arbitrary load address and RAM base detection2023-05-11T19:55:31ZKimplulkimi.h.kuparinen@gmail.com2023-05-11T19:55:31Zurn:sha1:27ffa747f36aee9c1d5bbc61395a078238366070
+ Both kind of go hand in hand, made sense to do both at the same time.
Some parts feel slightly hacky, the loader works by placing everything
on the stack and avoiding global values. Still, seems to work?
make cross compile more conformant2023-05-06T17:33:53ZKimplulkimi.h.kuparinen@gmail.com2023-05-06T17:33:53Zurn:sha1:6973772c26a0975e2df5623a705d91573b4bfd45riscv32 boots and advances as far as riscv642022-09-14T18:21:27ZKimplulkimi.h.kuparinen@gmail.com2022-09-11T18:50:55Zurn:sha1:025778e89e7d0fe3cd1ad53537c9cc6f3cd819cc